After system start-up, all CR16CAN related registers are in their reset state. The CR16CAN module can be enabled after all configuration registers are set to their desired value. The following initial setting need to be made:
— configure the CAN Timing register (CTIM) See “Bit Time Logic” on page 93.
— configure every buffer to its function as receive/trans-mit Buffer Status/Control Register (CNSTAT) on page 104.
— set the acceptance filtering masks. See “Acceptance Filtering” on page 95.
— enable the CR16CAN interface. See “CAN Global Con-figuration Register (CGCR)” on page 107.
Before disabling the CR16CAN module, the user has to make sure that no transmission is still pending.
Note: The device can be awaken from a power saving mode by an activity on the CAN bus by selecting the CAN RX pin as an input to the Multi-Input Wake-Up module. In this case the CR16CAN module must not be disabled before entering the power saving mode. Disabling the CR16CAN module also disables the CAN RX pin.
As an alternative, the CAN RX pin can be connected to any other input pin of the Multi-Input Wake-Up module. This input channel must then be configured to trigger a wake-up event on a falling edge (if a dominant bit is represented by a low level). In this case the CR16CAN module can be disabled be-fore entering a power saving mode. After the device has been waken up, the user has to manually enable the CR16CAN again. All configuration and buffer registers still contain the same data as prior to the power down phase.
20.10.1 External Connection
The CR16CAN uses two external pins, CANTX and CANRX to connect to the physical layer of the CAN interface. They provide the functionality as described in Table 38.
The logic levels are configurable by means of two control flags CTX and CRX of the Global Configuration Register CGCR (see “CAN Global Configuration Register (CGCR)” on page 107.
Figure 71. EBID Example
Table 38 External CR16CAN Pins Signal Name Type Description
CANTX Output Transmit data to the CAN bus CANRX Input Receive data from the CAN bus
20.10.2 Transceiver Connection
An external Transceiver Chip needs to be connected be-tween the CAN block and the bus. It is used to establish a bus connection in differential mode and furthermore provides the driver and protection requirements.
Figure 72 shows a possible ISO-High-Speed configuration
.
20.10.3 Timing Requirements
Processing messages and updating message buffers require a certain number of clock cycles by CR16CAN as shown in Table 39. These requirements may lead to some restrictions regarding the Bit Time Logic settings and the overall CR16CAN performance which are described below in more detail.
The critical path derives from receiving a remote frame which triggers the transmission of one or more data frames. There are a minimum of four bit times in-between two consecutive frames. These bit times start at the validation point of re-ceived frame (reception of 6th EOF bit) and end at the earli-est possible transmission start of the next frame, which is after the third intermission bit at 100% burst bus load.
These four bit times have to be set in perspective with the timing requirements of the CR16CAN.
The minimum duration of the four CAN bit times is deter-mined by the following Bit Time Logic settings:
PSC = PSCmin = 2 TSEG1 = TSEG1min = 2 TSEG2 = TSEG2min = 1
bit time = Synch + Time Segment 1 + Time Segment 2
= (1 + 2 + 1) tq = 4 tq
= (4 tq x PSC) clock cycles
= (4 tq x 2) clock cycles = 8 clock cycles
For these minimum BTL settings, four CAN bit times take 32 clock cycles.
The following is an example that assumes typical case:
— minimum BTL settings
— reception and copy of a remote frame
— update of one buffer from TX_RTR
— schedule of one buffer from transmit
As outlined in Table 39 the copy process, update and sched-uling the next transmission gives a total of 17+3+2=22 clock cycles. Therefore under these conditions there is no timing restriction.
The following example assumes the worst case:
— minimum BTL settings
— reception and copy of a remote frame
— update of the 14 remaining buffers from TX_RTR
— schedule of one buffer for transmit
All these actions in total require 17 + 14 x 3 + 2 = 61 clock cycles to be executed by CR16CAN. This leads to the limita-tion of the Bit Time Logic of 61 / 4 = 15.25 clock cycles per CAN bit as a minimum, resulting in the minimum clock fre-quencies listed below (the frequency depends on the desired baud rate and assumes the worst case scenario can occur in the application).
Table 40 gives examples for the minimum clock frequency in order to ensure proper functionality at various CAN bus speeds.
20.10.4 Bit Time Logic Calculation Examples
The calculation of the CAN bus clocks using CKI = 16MHz is shown in the following examples. The desired baud rate for both examples is 1Mbit/s.
Example 1
PSC = PSC[5:0] + 2 = 0 + 2 = 2 TSEG1 = TSEG1[3:0] + 1 = 3 + 1 = 4 TSEG2 = TSEG2[2:0] + 1 = 2 + 1 = 3 SJW = TSEG2 = 3
Table 39 CR16CAN Internal Timing
task # cycles a
a. Wait cycles need to be added for CPU access to the object memory as described in CPU Access to CR16CAN Registers/Memory on page 103.
occurrence/
frame b
b. Depends on the number of matching identifiers.
copy hidden buffer to receive
message buffer 17 0-1
update status from TX_RTR
to TX_ONCE_RTR 3 0-15
schedule a message for
trans-mission 2 0-1
Figure 72. External Transceiver Connection (ISO-High-Speed)
Table 40 Min. Clock Frequency Requirements Baud Rate min. clock frequency
1Mbit/sec 15.25MHz
500kbit/sec 7.625MHz
250kbit/sec 3,81MHz
— sample point positioned at 62.5% of bit time
— bit time = 125ns x (1 + 4 + 3 ± 3) = (1 ± 0.375)µs
— busclock = 16MHz / (2 x (1 + 4 + 3)) = 1Mbit/s (nominal) Example 2
PSC = PSC[5:0] + 1 = 2 + 2 = 4 TSEG1 = TSEG1[3:0] + 1 = 1 + 1 = 2 TSEG2 = TSEG2[2:0] + 1 = 0 + 1 = 1 SJW = TSEG2 = 1
• sample point positioned at 75% of bit time
• bit time = 250ns x (1 + 2 + 1 ± 1) = (1 ± 0.25)µs
• busclock = 16MHz / (2 x (1 + 4 + 3)) = 1Mbit/s (nominal) 20.10.5 Acceptance Filter Considerations
The CR16CAN provides two acceptance filter masks GMSK and BMSK as described in Acceptance Filtering on page 95, Global Mask Registers (GMSK — GMSKB and GMSKX) on page 110 and Basic Mask Registers (BMSK — BMSKB and BMSKX) on page 110. These masks allow filtering of up to 32 bits of the message object, which includes the standard identifier, the extended identifier as well as the frame control bits RTR, SRR and IDE.
20.10.6 Remote Frames
Remote frames can be automatically processed by the CR16CAN interface. However, to fully enable that feature, the RTR/XRTR bits (for both standard and extended frames) within the BMSK and/or GMSK register need to be set to
“don’t care”. This is because a remote frame with the RTR bit being set to “1” should trigger the transmission of a data frame with the RTR bit set to “0” and therefore the ID bits of the received message need to pass through the acceptance filter. The same applies to transmitting remote frames and switching to receive the corresponding data frames.
21.0 Analog Comparators
The Dual Analog Comparator (ACMP2) module contains two independent analog comparators with all necessary control logic. Each comparator unit compares the analog input volt-ages applied to two input pins and determines which voltage is higher. The comparison results can be placed on two out-put pins and/or read by the software from a register.
Figure 73 is a block diagram of the Dual Analog Comparator module.
The two comparators are designated Comparator 1 (CMP1) and Comparator 2 (CMP2). Each comparator has a positive and a negative input, called CMP1P and CMP1N for Com-parator 1 and CMP2P and CMP2N for ComCom-parator 2. An op-tional output, CMP1O for Comparator 1 or CMP2O for Comparator 2, allows the external hardware to read the com-parison results. If the positive input is greater than the nega-tive input, the result is a logic 1. Otherwise, the result is a logic 0. These same results are available to the software by reading the CMPCTRL register. CMP1OP and CMP2OP are the direct outputs of the analog comparator. These signals are connected to the channels of the Multi-Wake-Up module.