In order to transmit a CAN message, the user has to config-ure the message buffer by changing the buffer status to TX_NOT_ACTIVE. The buffer is configured for transmission if the ST[3] bit of the buffer status code (CNSTAT) is set to ‘1’.
In TX_NOT_ACTIVE status, the buffer is ready to receive data from the CPU. After receiving all transmission data (ID, data bytes, DLC and PRI), the CPU can start the transmis-sion by writing TX_ONCE into the buffer status register. Dur-ing the transmission the status of the buffer is TX_BUSYx.
After successful transmission CR16CAN will reset the buffer status to TX_NOT_ACTIVE. When the transmission process fails, the buffer condition will remain TX_BUSYx for re-trans-mission until the frame was successfully transmitted or the CPU has canceled the transmission request.
In order to Send a Remote Frame (Remote Transmission Request) to other CAN nodes, the user needs to set the RTR bit of the message identifier to “1” (see Storage of Remote Messages on page 107) and change the status of the mes-sage buffer to TX_ONCE. After this remote frame has been transmitted successfully, this message buffer will automati-cally enter the RX_READY state and is ready to receive the appropriate answer. Note that the mask bits RTR/XRTR need to be set to receive a data frame (RTR = 0) in a buffer which was configured to transmit a remote frame (RTR = 1).
To answer Remote Frames if the CPU writes TX_RTR in the buffer status register, the buffer will wait for a remote frame.
When a remote frame passes the acceptance filtering mask of one or more buffers, the buffer status will change to TX_ONCE_RTR, the contents of the buffer will be transmit-ted and afterwards CR16CAN will write TX_RTR in the status code register again.
If the CPU writes TX_ONCE_RTR in the buffer status, the contents of the buffer will be transmitted, and the successful transmission the buffer goes into the “wait for Remote Frame”
condition TX_RTR.
20.6.1 Transmit Scheduling
After writing TX_ONCE in the buffer status, the transmission process begins and the BUSY-bit is set. As soon as a buffer gets the TX_BUSY status, the buffer is not accessible any-more by the CPU except for the ST[3:1] bits of the CNSTAT register. Starting with the beginning of the CRC field of the current frame, CR16CAN looks for another buffer transmit re-quest and selects the buffer with the highest priority for the next transmission by changing the buffer state from TX_ONCE to TX_BUSY. This transmit request can be can-celed by the CPU or can be overwritten by another transmit request of a buffer with a higher priority as long as the trans-mission of the next frame has not yet started. This means that between the beginning of the CRC field of the current frame and the transmission start of the next frame, two buff-ers, the current buffer and the buffer scheduled for the next transmission, are in the BUSY status. In order to cancel the transmit request of the next frame, the CPU has to change the buffer state to TX_NOT_ACTIVE. When the transmit re-quest has been overwritten by another rere-quest of a higher priority buffer, CR16CAN changes the buffer state from TX_BUSY to TX_ONCE. Thus, the transmit request remains pending. Figure 64 further illustrates the transmit timing.
If the transmit process fails or the arbitration is lost, the trans-mission process will be stopped and will continue after the in-terrupting reception or the error signaling has finished (see Figure 65). In that case a new buffer select follows and the TX process is executed again.
Note: The canceled message can be delayed by a TX re-quest of a buffer with a higher priority. During TX_BUSY high, the user cannot change the contents of the message buffer object. In all cases writing to the BUSY bit will be ignored.
read buffer (id/data/cntrl)
write RX_READY
exit
Figure 63. Buffer Read Routine (BUFFLOCK Enabled) Interrupt Entry Point
clear RX_PND
20.6.2 Transmit Priority
CR16CAN is able to generate a stream of scheduled mes-sages without releasing the bus between two mesmes-sages so that an optimized performance can be achieved. It will arbi-trate for the bus right after sending the previous message and will only release the bus due to a lost arbitration.
If more than one buffer is scheduled for transmission, the pri-ority is built by the message buffer number and the pripri-ority code in the CNSTAT register. The 8-bit value of the priority is combined by the 4-bit TXPRI value and the 4-bit buffer num-ber (0...14) as shown below. The lowest resulting numnum-ber re-sults in the highest transmit priority.
Table 22 shows the transmit priority configuration if the prior-ity is set to TXPRI = 0 for all transmit buffers:
Table 23 shows the transmit priority configuration if TXPRI is different from the buffer number:
Note: If two buffers have the same priority (PRI), the buffer with the lower buffer number will have the higher priority.
TX_BUSY
begin selection of next buffer if new tx_request
current buffer TX_BUSY next buffer
SOF
ARBITRATION FIELD DATA FIELD (IF PRESENT)
CRC ACK
FIELD EOF
1 BIT 12/29 BIT + 6 BIT n * 8 BIT 16 BIT 2 BIT 7 BIT
FIELD IFS
3 BIT
Figure 64. Data Transmission + CONTROL
BUS IDLE
CPU write TX_ONCE in buffer status
Table 22 Transmit Priority (TXPRI=0)
TXPRI Buffer
Number PRI TX Priority
0 0 0 highest
0 1 1
: :
: :
: :
: :
0 14 14 lowest
TXPRI BUFFER #
Table 23 Transmit Priority (TXPRI not 0)
TXPRI Buffer
Number PRI TX Priority
14 0 224 lowest
13 1 209
12 2 194
11 3 179
10 4 164
9 5 149
8 6 134
7 7 119
6 8 104
5 9 89
4 10 74
3 11 59
2 12 44
1 13 29
0 14 14 highest
20.6.3 Transmit Procedure
The transmission of a CAN message has to be executed as follows (see also Figure 65)
1. Configure CNSTAT status field as TX_NOT_ACTIVE. If the status is TX_BUSY, a previous transmit request is still pending and the user has no access to the data con-tents of the buffer. In that case the user may choose to wait until the buffer becomes available again as shown.
Other options are to exit from the update routine until the buffer has been transmitted with an interrupt generated, or the transmission is aborted by an error.
2. Load buffer identifier & data registers. (For remote frames the RTR bit of the identifier needs to be set and loading data bytes can be omitted.)
3. Configure CNSTAT status field to the desired value:
— TX_ONCE to trigger the transmission process of a sin-gle frame.
— TX_ONCE_RTR to trigger the transmission of a single data frame and then wait for a received remote frame to trigger consecutive data frames.
— TX_RTR waits for a remote frame to trigger the trans-mission of a data frame.
Writing TX_ONCE or TX_ONCE_RTR in the CNSTAT status field will set the internal transmit request for the CR16CAN.
If a buffer is configured as TX_RTR and a remote frame is re-ceived, the data contents of the addressed buffer will be transmitted automatically without further CPU activity.
20.6.4 TX Buffer States
The transmission process can be started after the user has loaded the buffer registers (data, ID, DLC, PRI) and set the buffer status from TX_NOT_ACTIVE to TX_ONCE, TX_RTR or TX_ONCE_RTR.
When the CPU writes TX_ONCE, the buffer will be TX_BUSY as soon as CR16CAN has scheduled this buffer for the next transmission. After the frame could be success-fully transmitted, the buffer status will be automatically reset to TX_NOT_ACTIVE when a data frame was transmitted or to RX_READY when a remote frame was transmitted.
If the CPU configures the message buffer to TX_ONCE_RTR, it will transmit its data contents. During the transmission the buffer state is 11112 as the CPU wrote 11102 into the status section of the CNSTAT register. After the suc-cessful transmission the buffer enters the TX_RTR state and waits for a remote frame. When it receives a remote frame, it will go back into the TX_ONCE_RTR state, transmit its data bytes and return to TX_RTR. If the CPU writes 10102 into the buffer status section, it will only enter the TX_RTR state. But it will not send its data bytes before it waits for a remote frame. Figure 66 illustrates the possible transmit buffer states.
20.7 INTERRUPTS
CR16CAN has access to one interrupt vector in the CR16 CPU. The interrupt process can be initiated from the follow-ing sources.
• CAN data transfer
— Reception of a valid data frame in the buffer. (Buffer state changes from RX_READY to RX_FULL or RX_OVERRUN).
— Successful transmission of a data frame. (Buffer state changes from TX_ONCE to TX_NOT_ACTIVE or RX_READY)
— Successful response to a remote frame. (Buffer state changes from TX_ONCE_RTR to TX_RTR).
— Transmit scheduling. (Buffer state changes from TX_RTR to TX_ONCE_RTR).
• CAN error conditions is the detection of an CAN error.
(The CEIPND bit in the CIPND register will be set as well as the corresponding bits in the error diagnostic register CEDIAG).
The receive/transmit interrupt access to every message buff-er can be individually enabled/disabled in the CIEN registbuff-er.
The pending flags of the message buffer are located in the CIPND register (read only) and can be cleared by resetting the flags in the CICLR registers.
20.7.1 Highest Priority Interrupt Code
In order to reduce decoding time of the CIPND register, the buffer interrupt request with the highest priority is placed as interrupt status code into the IST[3:0] section of the CSTPND register.
write_buffer
TX_BUSYx? Y
N write
write ID/data
write
exit
Figure 65. Buffer Write Routine TX_ONCE
or TX_ONCE_RTR
or TX_RTR TX_NOT_ACTIVE
(see text)
Each of the buffer interrupts as well as the error interrupt can be individually enabled or disabled in the CAN Interrupt En-able register (CIEN). As soon as an interrupt condition oc-curs, every interrupt request is indicated by a flag in the CAN Interrupt Pending register (CIPND). When the interrupt code logic for the present highest priority interrupt request is en-abled, this interrupt will be translated into the IST[3:0] bits of the CAN Status Pending register (CSTPND). An interrupt re-quest can be cleared by setting the corresponding bit in the CAN Interrupt Clear register (CICLR) to ‘1’.
Figure 67 illustrates the CR16CAN interrupt management.
Figure 66. Transmit Buffer States TX_ONCE
TX_NOT_ACTIVE
RX_READY
TX done
request cancelled
Remote transmission TX_RTR
RTR
CPU writes 1010
transmit failed CAN
TX_BUSY0 TX_ONCE_RTR
TX_BUSY2
TX done CAN schedules TX
transmit
transmit request cancelled
transmit failed received
CPU writes 1100 TX request
TX request CPU writes 1110
CPU writes 1000 CPU writes 1000
schedules TX 1110
1111
1010 1000
1100
0010
1101
*1
*1: TX request delayed by a TX request of higher priority message
request sent - now wait to receive a data frame
Figure 67. CR16CAN Interrupt Management CIPND
IST0 IST1 IST2 IST3
ICODE
clear interrupt flags of every
IRQ CICLR
CIEN
CICEN
message buffer individually
The highest priority interrupt source is translated into the bits IRQ and IST[3:0] as shown in Table 24.
20.7.2 Usage Hints
The interrupt code IST[3:0] can be used within the interrupt handler as a displacement in order to jump to the relevant subroutine.
The CAN Interrupt Code Enable (CICEN) register is used in the CAN interrupt handler if the user wants to service all re-ceive buffer interrupts first followed by all transmit buffer in-terrupts. In this case, the user can first enable only all receive buffer interrupts to be coded, scan and service all pending in-terrupt requests in the order of their priority. Then, the user changes the CICEN register to disable all receive buffers, but enable all transmit buffers and service all pending transmit buffer interrupt requests according to their priorities.