The Versatile-Timer-Unit (VTU) is comprised of four timer subsystems. Each timer subsystem contains an 8-bit clock prescaler, a 16-bit up-counter and two 16-bit registers. Each timer subsystem controls two I/O pins which either function as PWM outputs or capture inputs depending on the mode of operation. There are four system level interrupt requests, one for each timer subsystem. Each system level interrupt re-quest is controlled by four interrupt pending flags with asso-ciated enable/disable bits. All four timer subsystems are fully independent and each may operate as a dual 8-bit PWM tim-er, a 16-bit PWM timer or as a dual 16-bit capture timer. Fig-ure 18 illustrates the main elements of the Versatile-Timer-Unit (VTU).
I/O control I/O control
TIO3 TIO4
I/O control I/O control
TIO5 TIO6
I/O control I/O control
TIO7 TIO8
I/O control I/O control
TIO1 TIO2
Timer Subsystem 1 Timer Subsystem 2 Timer Subsystem 3 Timer Subsystem 4
MODE
Figure 18. VTU Block Diagram
16.1.1 Dual 8-bit PWM Mode
Each timer subsystem may be configured to generate two fully independent PWM waveforms on the respective TIOx pins. In this mode, the counter COUNTx is split and operates as two independent 8-bit counters. Each counter increments at the rate determined by the clock prescaler.
Each of the two 8-bit counters may be started and stopped separately via the associated TxRUN bits. Once either of the two 8-bit timers is running the clock prescaler starts counting.
Once the clock prescaler counter value matches the value of the associated CxPRSC register field, COUNTx is incre-mented.
The period of the PWM output waveform is determined by the value of the PERCAPx register. The TIOx output starts at the default value as pro-grammed via the IOxCTL.PxPOL bit.
Once the counter value reaches the value of the period reg-ister PERCAPx, the counter is reset to 0016 upon the next counter increment. Upon the following increment from 0016 to 0116, the TIOx output will change to the opposite of the de-fault value.
The duty cycle of the PWM output waveform is controlled by the DTYCAPx register value. Once the counter value reach-es the value of the duty cycle register DTYCAPx, the PWM output TIOx changes back to its default value upon the next counter increment. Figure 19 illustrates this concept.
The period time is determined by the following formula:
PWMperiod = (PERCAPx + 1) * (CxPRSC + 1) * TCLK The duty cycle in percent is calculated as follows:
DutyCycle[%] = (DTYCAPx / (PERCAPx+1)) *100 If the duty cycle register (DTYCAPx) holds a value which is greater then the value held in the period register (PERCAPx) the TIOx output will remain at the opposite of its default value which corresponds to a duty cycle of 100%. If the duty cycle register (DTYCAPx) register holds a value of 0016, the TIOx output will remain at the default value which corresponds to a duty cycle of 0%. In that case the value contained in the PERCAPx register is irrelevant. This scheme allows the duty cycle to be programmed in a range from 0% to 100%.
In order to allow fully synchronized updates of the period and duty cycle compare values, the PERCAPx and DTYCAPx registers are double buffered when operating in PWM mode.
Therefore if the user writes to either the period or duty cycle
register while either of the two PWM channels is enabled, the new value will not take effect until the counter value matches the previous period value or the timer is stopped.
Reading the PERCAPx or DTYCAPx register will always re-turn the most recent value written to it.
The counter registers can be written if both 8-bit counters are stopped. This allows the user to preset the counters before starting and therefore generate PWM output waveforms with a phase shift relative to one another. If the counter is written with a value other then 0016 it will start incrementing from that value while TIOx remains at its default value until the first 0016 to 0116 transition of the counter value occurs. If the counter is preset to values which are smaller or equal then the value held in the period register (PERCAPx) the counter will count up until a match between the counter value and the PERCAPx register value occurs. The counter will then be re-set to 0016 and continue counting up. Alternatively the counter may be written with a value which is greater then the 00
COUNTx PERCAPx
DTYCAPx
TIOx (PxPOL=0)
TIOx (PxPOL=1) TxRUN=1
01
00 01
02 03
04 05
06 07
08 09
0A
02 03
04 05
06 07
08 09
0A
Figure 19. VTU PWM generation
value held in the period register. In that case the counter will count up to FF16 and then roll over to 0016. In any case the TIOx pin always changes its state at the 0016 to 0116 transi-tion of the counter.
The user software may only write to the COUNTx register if both TxRUN bits of a timer subsystem are cleared. Any writes to the counter register while either timer is running will be ignored.
The two I/O pins associated with a timer subsystem function as independent PWM outputs in the dual 8-bit PWM mode. If a PWM timer is stopped via its associated MODE.TxRUN bit the following actions result:
— The associated TIOx pin will return to its default value as defined by the IOxCTL.PxPOL bit.
— The counter will stop and will retain its last value.
— Any pending updates of the PERCAPx and DTYCAPx register will be completed.
— The prescaler counter will be stopped and reset if both MODE.TxRUN bits are cleared.
Figure 20 illustrates the configuration of a timer subsystem while operating in dual 8-bit PWM mode. The numbering in Figure 20 refers to timer subsystem 1 but equally applies to the other three timer subsystems.
16.1.2 16-Bit PWM Mode
Each of the four timer subsystems may be independently configured to provide a single 16-bit PWM channel. In this case the lower and upper bytes of the counter are concate-nated to form a single 16-bit counter.
Operation in 16-bit PWM mode is conceptually identical to the dual 8-bit PWM operation as outlined under Dual 8-bit PWM Mode on page 59. The 16-bit timer may be started or stopped with the lower MODE.TxRUN bit, i.e. T1RUN for tim-er subsystem 1.
The two TIOx outputs associated with a timer subsystem can be used to produce either two identical PWM waveforms or two PWM waveforms of opposite polarities. This can be ac-complished by setting the two PxPOL bits of the respective timer subsystem to either identical or opposite values.
Figure 21 illustrates the configuration of a timer subsystem while operating in 16-bit PWM mode. The numbering in Figure 21 refers to timer subsystem 1 but equally applies to the other three timer subsystems.
Figure 21. VTU 16-bit PWM Mode 16.1.3 Dual 16-Bit Capture Mode
In addition to the two PWM modes, each timer subsystem may be configured to operate in an input capture mode which provides two 16-bit capture channels. The input capture mode can be used to precisely measure the period and duty cycle of external signals.
In capture mode the counter COUNTx operates as a 16-bit up-counter while the two TIOx pins associated with a timer subsystem operate as capture inputs. A capture event on the TIOx pins causes the contents of the counter register (COUNTx) to be copied to the PERCAPx or DTYCAPx regis-ters respectively.
Starting the counter is identical to the 16-bit PWM mode, i.e.
setting the lower of the two MODE.TxRUN bits will start the counter and the clock prescaler. In addition, the capture event inputs are enabled once the MODE.TxRUN bit is set.
The TIOx capture inputs can be independently configured to detect a capture event on either a positive transition, a neg-ative transition or both a positive and a negneg-ative transition. In addition, any capture event may be used to reset the counter COUNTx and the clock prescaler counter. This avoids the need for the user software to keep track of timer overflow conditions and greatly simplifies the direct frequency and duty cycle measurement of an external signal.
Figure 22 illustrates the configuration of a timer subsystem while operating in capture mode. The numbering in Figure 22
Prescaler
Figure 20. VTU Dual 8-bit PWM Mode
Prescaler
refers to timer subsystem 1 but equally applies to the other three timer subsystems.
Figure 22. VTU Dual 16-bit Capture Mode 16.1.4 Low Power Mode
In case a timer subsystem is not used, the user can place it in a low-power-mode. All clocks to a timer subsystem are stopped and the counter and prescaler contents are frozen once low-power-mode is entered. The user may continue to write to the MODE, INTCTL, IOxCTL and CLKxPS registers.
Write operations to the INTPND register are allowed; but if a timer subsystem is in low power mode, its associated inter-rupt pending bits cannot be cleared. The user cannot write to the COUNTx, PERCAPx and DTYCAPx registers of a timer subsystem while it is in low-power-mode. All registers can be read at any time.
16.1.5 Interrupts
The Versatile-Timer-Unit (VTU) has a total of 16 interrupt sources, four for each of the four timer subsystems. All inter-rupt sources have a pending flag and an enable bit
associat-ed with them. All interrupt pending flags are denotassociat-ed IxAPD through IxDPD where “x” relates to the specific timer sub-system. There is one system level interrupt request for each of the four timer subsystems.
Figure 23 illustrates the interrupt structure of the versatile timer module.
Figure 23. VTU Interrupt Request Structure Each of the timer pending flags - IxAPD through IxDPD - is set by a specific hardware event depending on the mode of operation, i.e., PWM or Capture mode. Table 17 outlines the specific hardware events relative to the operation mode which cause an interrupt pending flag to be set.
16.1.6 ISE Mode operation
The VTU supports breakpoint operation of the In-System-Emulator (ISE). If FREEZE is asserted, all timer counter clocks will be inhibited and the current value of the timer reg-isters will be frozen; in capture mode, all further capture events are disabled. Once FREEZE becomes inactive, counting will resume from the previous value and the capture input events are re-enabled.