IRF250-2

File Number 1825.3

30A, 200V, 0.085 Ohm, N-Channel Power MOSFET

This N-Channel enhancement mode silicon gate power field effect transistor is designed, tested and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. These MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. They can be operated directly from integrated circuits.

Formerly developmental type TA09295.

Features

• 30A, 200V

• r_DS(ON)= 0.085Ω

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”

Symbol

Packaging

JEDEC TO-204AE TOP VIEW

Ordering Information

PART NUMBER PACKAGE BRAND

IRF250 TO-204AE IRF250

NOTE: When ordering, include the entire part number.

G

D

S

DRAIN (FLANGE)

SOURCE (PIN 2) GATE (PIN 1)

Data Sheet March 1999

Absolute Maximum Ratings

IRF250 UNITS

Drain to Source Voltage (Note 1) . . . .V_DS 200 V Drain to Gate Voltage (R_GS = 20kΩ)(Note 1) . . . V_DGR 200 V Continuous Drain Current . . . I_D 30 A T_C = 100^oC . . . I_D 19 A Pulsed Drain Current (Note 3) . . . I_DM 120 A Gate to Source Voltage . . . .V_GS ±20 V Maximum Power Dissipation . . . .P_D 150 W Linear Derating Factor . . . 1.2 W/^oC Single Pulse Avalanche Energy Rating (Note 4) . . . .E_AS 910 mJ Operating and Storage Temperature . . . T_J, T_STG -55 to 150 ^oC Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s . . . T_L Package Body for 10s, See Techbrief 334 . . . T_pkg

300 260

oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. T_J = 25^oC to 125^oC.

Electrical Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV_DSS V_GS = 0V, I_D = 250µA (Figure 10) 200 - - V

Gate Threshold Voltage V_GS(TH) V_GS = V_DS, I_D = 250µA 2.0 - 4.0 V

Zero Gate Voltage Drain Current I_DSS V_DS = Rated BV_DSS, V_GS = 0V - - 25 µA

V_DS = 0.8 x Rated BV_DSS, V_GS = 0V, T_J = 125^oC - - 250 µA

On State Drain Current (Note 2) I_D(ON) V_DS> I_{D(ON) x}r_DS(ON)MAX, V_GS = 10V 30 - - A

Gate to Source Leakage Current I_GSS V_GS =±20V - - ±100 nA

Drain to Source On Resistance (Note 2) r_DS(ON) V_GS = 10V, I_D = 16A (Figures 8, 9) - 0.07 0.085 Ω

Forward Transconductance (Note 2) g_fs V_DS≥ 50V, ID = 16V (Figure 12) 13 19 - S

Turn-On Delay Time t_D(ON) V_DD= 100V, I_D≈ 30A, RG = 6.2Ω, R_L = 3.2Ω (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature

- 20 30 ns

Rise Time t_r - 120 180 ns

Turn-Off Delay Time t_D(OFF) - 70 100 ns

Fall Time t_f - 80 120 ns

Total Gate Charge

(Gate to Source + Gate to Drain)

Q_g(TOT) V_GS = 10V, I_D = 30A, V_DS = 0.8 x Rated BV_DSS, I_g(REF)= 1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature

- 79 120 nC

Gate to Source Charge Q_gs - 13 - nC

Gate to Drain “Miller” Charge Q_gd - 42 - nC

Input Capacitance C_ISS V_GS = 0V, V_DS = 25V, f = 1.0MHz (Figure 11) - 2000 - pF

Output Capacitance C_OSS - 800 - pF

Reverse-Transfer Capacitance C_RSS - 300 - pF

Internal Drain Inductance L_D Measured between the

Contact Screw on Header that is Closer to Source and Gate Pins and Center of Die

Modified MOSFET Symbol Showing the Internal Devices Inductances

- 5.0 - nH

Internal Source Inductance L_S Measured from the

Source Lead, 6mm (0.25in) from Header to Source Bonding Pad

- 12.5 - nH

Thermal Resistance Junction to Case R_θJC - - 0.83 ^oC/W

Thermal Resistance Junction to Ambient R_θJA Free Air Operation - - 30 ^oC/W

L_S L_D

G

D

S

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I_SD Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode

- - 30 A

Pulse Source to Drain Current (Note 3) I_SDM - - 120 A

Source to Drain Diode Voltage (Note 2) V_SD T_J = 25^oC, I_SD= 30A, V_GS = 0V (Figure 13) - - 2.0 V

Reverse Recovery Time t_rr T_J = 25^oC, I_SD = 30A, dI_SD/dt = 100A/µs 140 350 630 ns

Reverse Recovered Charge Q_RR T_J = 25^oC, I_SD = 30A, dI_SD/dt = 100A/µs 1.8 4.7 8.1 µC

NOTES:

2. Pulse Test: Pulse width≤ 300µs, duty cycle≤ 2%.

3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. V_DD = 50V, starting T_J = 25^oC, L = 1.5mH, R_G = 25Ω, peak I_AS = 30A. See Figures 15 and 16.

Typical Performance Curves

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE G

D

S

0 50 100 150

0

T_C, CASE TEMPERATURE (^oC)

POWER DISSIPATION MULTIPLIER

0.2 0.4 0.6 0.8 1.0 1.2

T_C, CASE TEMPERATURE (^oC)

50 75 100

25 150

40

32

24

0 16

ID,DRAIN CURRENT (A) 8

125

ZθJC, THERMAL IMPEDANCE 1

10^-2

10^-5 10^-4 10^-3 0.1 1 10

t₁, RECTANGULAR PULSE DURATION (S) 0.1

10^-2

10^-3 0.02 0.01 0.05 0.2 0.5

0.1

SINGLE PULSE

DUTY FACTOR: D = t₁/t₂ NOTES:

PEAK T_J= P_DM x Z_θJC + T_C t₂ P_DM

t₁ t₂

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves

10

1.0 10

0.1 ID, DRAIN CURRENT (A)

V_DS, DRAIN TO SOURCE VOLTAGE (V) 10³

1

OPERATION IN THIS REGION IS LIMITED BY r_DS(ON)

T_J = MAX RATED SINGLE PULSE T_C = 25^oC

1ms 10ms

DC 100ms 10² 10ms

10² 10³

V_DS, DRAIN TO SOURCE VOLTAGE (V)

20 40 60 80

0 50

40

30

0 20

ID, DRAIN CURRENT (A) 10

V_GS = 7V

100 V_GS = 10V

V_GS = 5V

V_GS = 4V V_GS = 6V

80µs PULSE TEST

V_DS, DRAIN TO SOURCE VOLTAGE (V)

1 2 3 4

0 5

50

40

30

0 20

ID, DRAIN CURRENT (A)

80µs PULSE TEST

10

V_GS = 10V

V_GS = 6V

V_GS = 4V V_GS = 8V

V_GS = 7V

V_GS = 5V

IDS(ON), DRAIN TO SOURCE CURRENT (A)

V_SD, GATE TO SOURCE VOLTAGE (V) 100

10

1

0.1

0 2 4 6 8 10

80µs PULSE TEST V_DS≥ 50V

T_J = 150^oC T_J = 25^oC

100 I_D, DRAIN CURRENT (A)

25 50 75

0 0.5

0.4

0 rDS(ON), DRAIN TO SOURCE

0.2

80µs PULSE TEST

ON RESISTANCE (Ω)

0.1

125 0.3

V_GS = 20V V_GS = 10V

0 3.0

1.8

0.6

100 T_J, JUNCTION TEMPERATURE (^oC)

NORMALIZED DRAIN TO SOURCE

2.4

1.2

0 140

ON RESISTANCE VOLTAGE

-40 40

-60 -20 20 60 80 120 120

I_D = 30A V_GS = 10V

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves

140 1.25

1.05

0.85

T_J, JUNCTION TEMPERATURE (^oC)

NORMALIZED DRAIN TO SOURCE

1.15

0.95

0.75

BREAKDOWN VOLTAGE

0 100

I_D = 250µA

-40 40

-60 -20 20 60 80 120 120 1 2 10 2 5 10²

C, CAPACITANCE (pF)

V_DS, DRAIN TO SOURCE VOLTAGE (V) 7500

6000

4500

3000

1500

0 5

C_RSS C_ISS

C_OSS V_GS = 0V, f = 1MHz C_ISS = C_GS + C_GD C_RSS = C_GD C_OSS≈ C_DS + C_GD

I_D, DRAIN CURRENT (A)

10 20 30 40

0 50

25

20

15

0 10

gfs, TRANSCONDUCTANCE (S) 5

T_J = 25^oC

T_J = 150^oC 80µs PULSE TEST

V_DS≥ 50V

ISD, SOURCE TO DRAIN CURRENT (A)

V_SD, SOURCE TO DRAIN VOLTAGE (V) 10²

10 0.5 1.0 1.5 2.5

10 2

2 5 5

T_J = 150^oC

T_J = 25^oC 10³

2

5

2.0

Q_g(TOT), TOTAL GATE CHARGE (nC)

25 50 75 100

0 125

20

8

VGS, GATE TO SOURCE VOLTAGE (V) 16 12

0

V_DS = 40V

4

I_D = 30A

V_DS = 100V

V_DS = 160V

Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS t_P

V_GS

0.01Ω L

I_AS

+

-

V_DS

V_DD R_G

DUT VARY t_P TO OBTAIN

REQUIRED PEAK I_AS

0V

V_DD V_DS BV_DSS

t_P

I_AS

t_AV 0

V_GS

R_L

R_G

DUT +

-

V_DD

t_ON t_d(ON)

t_r 90%

10%

V_DS

90%

10%

t_f t_d(OFF)

t_OFF

90%

50%

50%

10% PULSE WIDTH

V_GS 0

0

0.3µF 12V

BATTERY 50kΩ

V_DS S

DUT D

G

I_g(REF) 0

(ISOLATED V_DS

0.2µF

CURRENT REGULATOR

I_D CURRENT SAMPLING I_G CURRENT

SAMPLING

SUPPLY)

RESISTOR RESISTOR SAME TYPE AS DUT

Q_g(TOT) Q_gd Q_gs

V_DS

0

V_GS V_DD

I_g(REF)

0

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