IRF150-2

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File Number 1824.3

40A, 100V, 0.055 Ohm, N-Channel Power MOSFET

This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power.

These types can be operated directly from integrated circuits.

Formerly Developmental Type TA17421.

Features

• 40A, 100V

• r_DS(ON)= 0.055Ω

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”

Symbol

Packaging

JEDEC TO-204AE

Ordering Information

PART NUMBER PACKAGE BRAND

IRF150 TO-204AE IRF150

NOTE: When ordering, include the entire part number.

G

D

S

DRAIN (FLANGE)

SOURCE (PIN 2) GATE (PIN 1)

Data Sheet March 1999

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Absolute Maximum Ratings

T_C = 25^oC, Unless Otherwise Specified

IRF150 UNITS

Drain to Source Voltage (Note 1) . . . .V_DS 100 V Drain to Gate Voltage (R_GS = 20kΩ)(Note 1) . . . V_DGR 100 V Continuous Drain Current . . . ID 40 A T_C = 100ôC . . . I_D 25 A Pulsed Drain Current (Note 3) . . . I_DM 160 A Gate to Source Voltage . . . .V_GS ±20 V Maximum Power Dissipation . . . .P_D 150 W Linear Derating Factor . . . 1.2 W/ôC Single Pulse Avalanche Energy Rating (Note 4) . . . .E_AS 150 mJ Operating and Storage Temperature . . . T_J, T_STG -55 to 150 ôC Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s . . . T_L Package Body for 10s, See Techbrief 334 . . . T_pkg

300 260

oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. T_J = 25^oC to 125^oC.

Electrical Specifications

T_C = 25^oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV_DSS V_GS = 0V, I_D = 250µA (Figure 10) 100 - - V

Gate to Threshold Voltage V_GS(TH) V_GS = V_DS, I_D = 250µA 2.0 - 4.0 V

Zero Gate Voltage Drain Current I_DSS V_DS = Rated BV_DSS, V_GS = 0V - - 25 µA

V_DS = 0.8 x Rated BV_DSS, V_GS = 0V, T_J = 125^oC - - 250 µA

On-State Drain Current (Note 2) I_D(ON) V_DS> I_{D(ON) x}r_DS(ON)MAX, V_GS = 10V 40 - - A

Gate to Source Leakage Current I_GSS V_GS =±20V - - ±100 nA

Drain to Source On Resistance (Note 2) r_DS(ON) V_GS = 10V, I_D = 20A (Figures 8, 9) - 0.045 0.055 Ω Forward Transconductance (Note 2) g_fs V_DS> I_{D(ON) x}r_DS(ON)MAX, I_D = 20A (Figure 12) 9.0 11 - S Turn-On Delay Time t_d(ON) V_DD= 24V, I_D≈20A, R_G = 4.7Ω, RL = 1.2Ω

(Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature

- - 35 ns

Rise Time t_r - - 100 ns

Turn-Off Delay Time t_d(OFF) - - 125 ns

Fall Time t_f - - 100 ns

Total Gate Charge

(Gate to Source + Gate to Drain)

Q_g(TOT) V_GS = 10V, I_D = 50A, V_DS = 0.8 x Rated BV_DSS, I_g(REF)= -1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating

Temperature

- 63 120 nC

Gate to Source Charge Q_gs - 27 - nC

Gate to Drain “Miller” Charge Q_gd - 36 - nC

Input Capacitance C_ISS V_GS = 0V, V_DS = 25V, f = 1.0MHz (Figure 11) - 2000 - pF

Output Capacitance C_OSS - 1000 - pF

Reverse Transfer Capacitance C_RSS - 350 - pF

Internal Drain Inductance L_D Measured between the

Contact Screw on the Flange that is Closer to Source and Gate Pins and the Center of Die

Modified MOSFET Symbol Showing the Internal Devices Inductances

- 5.0 - nH

Internal Source Inductance L_S Measured from the

Source Lead, 6mm (0.25in) from the Flange and the Source Bonding Pad

- 12.5 - nH

Thermal Impedance Junction to Case R_θJC - - 0.8 ^oC/W

Thermal Impedance Junction to Ambient R_θJA Free Air Operation - - 30 ^oC/W

L_S L_D

G

D

S

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Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to DrainCurrent I_SD Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode

- - 40 A

Pulse Source to Drain Current (Note 3) I_SDM - - 160 A

Diode Source to Drain Voltage (Note 2) V_SD T_J = 25^oC, I_SD= 40A, V_GS = 0V (Figure 13) - - 2.5 V

Reverse Recovery Time t_rr T_J = 150^oC, I_SD = 40A, dI_SD/dt = 100A/µs - 600 - ns

Reverse Recovery Charge Q_RR T_J = 25^oC, I_SD = 5.5A, dI_SD/dt = 100A/µs - 3.3 - µC

NOTES:

2. Pulse test: pulse width≤ 300µs, duty cycle≤ 2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. V_DD = 10V, starting T_J = 25^oC, L = 170µH, R_G = 50Ω, Peak I_AS = 40A. See Figures 15, 16.

Typical Performance Curves

Unless Otherwise Specified

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE G

D

S

0 50 100 150

0

T_C, CASE TEMPERATURE (^oC)

POWER DISSIPATION MULTIPLIER

0.2 0.4 0.6 0.8 1.0 1.2

T_C, CASE TEMPERATURE (^oC)

50 75 100

25 150

40

32

24

0 16

ID,DRAIN CURRENT (A) 8

125

1.0

0.1

10^-2

10^-5 10^-4 10^-3 0.1 1 10

t₁, RECTANGULAR PULSE DURATION (s) ZθJC, TRANSIENT THERMAL

0.01

SINGLE PULSE

DUTY FACTOR: D = t₁/t₂ t₂ P_DM

t₁

NOTES:

0.5

T_J = P_DM x Z_θJC + T_C t₂ 0.01

0.2 0.1

0.02 0.05 IMPEDANCE (oC/W)

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FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

NOTE: Heating effect of 2µs is minimal.

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves

Unless Otherwise Specified (Continued)

10²

10

1 10 10²

1 ID, DRAIN CURRENT (A)

V_DS, DRAIN TO SOURCE VOLTAGE (V)

10³ 10³

SINGLE PULSE T_C = 25^oC

OPERATION IN THIS REGION IS LIMITED BY r_DS(ON)

T_J = MAX RATED

10µs100µs 1ms

DC 10ms 100ms

10 20 30 40

0 50

50

40

30

0 20

ID, DRAIN CURRENT (A)

7V

6V V_GS = 8V

5V

80µs PULSE TEST

10 10V 9V

4V

0.4 0.8 1.2 1.6

0 2.0

20

16

12

0 8

4

8V

6V

5V V_GS = 10V

4V 7V

9V

V_GS, GATE TO SOURCE VOLTAGE (V) 20

10

0

0 1 2 3 4 8

T_J = 125^oC

T_J = 25^oC

5 15 25 30

T_J = -55^oC 80µs PULSE TEST

V_DS > I_D(ON)x r_DS(ON)MAX

5 6 7

I_D, DRAIN CURRENT (A)

40 80 120

0 160

0.20

0.14

0.10

0.06 rDS(ON), DRAIN TO SOURCE

V_GS = 20V

0.02

V_GS = 10V

ON RESISTANCE (Ω)

2.2

1.4

0.6

80 -60

T_J, JUNCTION TEMPERATURE (^oC)

NORMALIZED DRAIN TO SOURCE

1.8

1.0

0.2 0 60 120

ON RESISTANCE

-20

-40 20 40 100 140

I_D = 14A V_GS = 10V

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FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves

Unless Otherwise Specified (Continued) 1.25

1.05

0.85

60

T_J, JUNCTION TEMPERATURE (^oC)

NORMALIZED DRAIN TO SOURCE

1.15

0.95

0.75 -20 20 100 160

BREAKDOWN VOLTAGE

0

-40 40 80 120 140

I_D = 250µA

0 10 30 40 50

C, CAPACITANCE (pF)

V_DS, DRAIN TO SOURCE VOLTAGE (V) 4000

3200

2400

1600

800

0 20

C_RSS C_ISS

C_OSS

V_GS = 0V, f = 1MHz C_ISS = C_GS + C_GD C_RSS = C_GD C_OSS≈ C_DS + C_GD

I_D, DRAIN CURRENT (A)

10 20 30 40

0 50

20

16

12

0 8

gfs, TRANSCONDUCTANCE (S)

4

T_J = -55ôC T_J = 25ôC T_J = 125ôC

ISD, SOURCE TO DRAIN CURRENT (A)

V_SD, SOURCE TO DRAIN VOLTAGE (V) 10²

10

1.0

0 1 2 3 4

T_J = 25^oC T_J = 150^oC

2

Q_g(TOT), TOTAL GATE CHARGE (nC)

28 56 84 112

0 140

5 20

10

VGS, GATE TO SOURCE VOLTAGE (V)

V_DS = 20V 15

0

I_D = 40A

FOR TEST CIRCUIT, SEE FIGURE 19

V_DS = 80V V_DS = 50V

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Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS t_P

V_GS

0.01Ω L

I_AS

+

-

V_DS

V_DD R_G

DUT VARY t_P TO OBTAIN

REQUIRED PEAK I_AS

0V

V_DD V_DS BV_DSS

t_P

I_AS

t_AV 0

V_GS

R_L

R_G

DUT +

-

V_DD

t_ON t_d(ON)

t_r 90%

10%

V_DS

90%

10%

t_f t_d(OFF)

t_OFF

90%

50%

10% PULSE WIDTH

V_GS 0

0

0.3µF 12V

BATTERY 50kΩ

V_DS S

DUT D

G

I_g(REF) 0

(ISOLATED V_DS

0.2µF

CURRENT REGULATOR

I_D CURRENT SAMPLING I_G CURRENT

SAMPLING

SUPPLY)

RESISTOR RESISTOR SAME TYPE AS DUT

Q_g(TOT) Q_gd Q_gs

V_DS

0

V_GS V_DD

I_G(REF)

0

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