Simulation of single-electron tunnelling circuits using SPICE

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Simulation of single-electron tunnelling

circuits using SPICE

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Simulation of single-electron tunnelling

circuits using SPICE

Proefschrift

ter verkrijging van de graad van doctor aan de Technische Universiteit Delft,

op gezag van de Rector Magnificus prof.dr.ir. J.T. Fokkema, voorzitter van het College voor Promoties,

in het openbaar te verdedigen op vrijdag 15 oktober 2004 om 13:00 uur

door

Rudie VAN DE HAAR

elektrotechnisch ingenieur geboren te Heemstede.

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Dit proefschrift is goedgekeurd door de promotor: Prof. dr. J.R. Long

Samenstelling promotiecommissie: Rector Magnificus, voorzitter

Prof. dr. J.R. Long TU Delft, promotor

Dr. J. Hoekstra TU Delft, toegevoegd promotor Prof. dr. ir. P.M. Dewilde TU Delft

Prof. dr. ir. A.H.M. van Roermund TU Eindhoven Prof. dr. J.N. Burghartz TU Delft Prof. dr. ir. G.C.M. Meijer TU Delft Prof. dr. S. Vassiliadis TU Delft

ISBN 90-9018050-8 NUG 959

Copyright c° 2004 by R. van de Haar

No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording or by any information storage and retrieval system, without written permission from the author.

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Index of symbols

Constants

symbol parameter value unit

e elementary charge 1.602177 · 10−19 _C

h Planck’s constant 6.6260755 · 10−34 _Js

kB Boltzmann’s constant 1.380658 · 10−23 J/K RK quantum resistance 25.8 · 103 Ω

Variables

symbol parameter unit

v(t) potential difference V i(t) current A q(t) charge C u(t) potential V P (t) power W E(t) energy J

SET junction model parameters

symbol parameter unit

CTJ tunnel capacitor F RT tunnel resistor Ω Γ tunnel rate s−1 vcr _{critical voltage} _V ∆t tunnel-time s ∆tλ stochastic wait-time s T temperature K

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x CONTENTS

Prefixes

prefix name value Y Yotta 1024 Z Zetta 1021 E Exa 1018 P Peta 1015 T Tera 1012 G Giga 109 M Mega 106 k kilo 103 - - 100 m milli 10−3 µ micro 10−6 n nano 10−9 p pico 10−12 f femto 10−15 a atto 10−18 z zepto 10−21 y yocto 10−24 Step function ²(t − t0) =      0 t < t0 undefined t = t0 1 t > t₀ Delta function δ(t − t0) = _dtd ²(t − t0) t ∈ R ∞ R −∞ δ(t)dt = 1 t ∈ R δ(t − t0) = 0 t ∈ R \{t0}

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Chapter 1

Introduction

In general, the ongoing challenges for both digital and analog electronics is to decrease the power consumption and to increase the maximum clock frequency or bandwidth of electronic circuits. Another challenge is to increase the num-ber of logic functions or storage cells which can be integrated onto a single chip. The following example is given to show that a fundamental limit for speed and power consumption of Complementary Metal Oxide Semiconductor (CMOS) technology is coming in sight. The dissipated energy during a single transition of a basic CMOS inverter is given by equation 1.1:

E_diss= 1

2 Cload (vDD− vSS)

2 _(1.1)

where Cload equals the capacitive load value and vDD and vSS are respectively

the positive and the negative supply voltages [1].

From this equation it is clear that in order to reduce the dissipated energy

E_diss, the supply voltage level vDD - vSS and the load capacitance value Cload, should be reduced. The current through the transistors iD (not explicitly

shown in equation 1.1) should then also be reduced. However, in order to de-crease the transition (or switching) time, the current through the transistors

iD should be increased in order to charge c.q. discharge the load capacitance Cload in less time. For the same reason, the load capacitance Cload should be reduced. Often C_load consists of the input capacitance of a following CMOS stage. The supply voltage level vDD - vSS should also be reduced. However,

there is a fundamental limit for reducing the supply voltage level vDD - vSS,

which is given by the transistor threshold voltage vt. This threshold voltage

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2 Introduction

A realistic value for v_t for a Negative-channel Metal Oxide Semiconductor (NMOS) [2] transistor is 250mV [3].

The two statements about power reduction and decreasing the transition (or switching) time, have in common that both the supply voltage level vDD - vSS

as the input capacitance Cin should be reduced.

A possible solution in order to reduce the supply voltage level vDD - vSS and to

reduce the input capacitance Cin, is to scale down the size of the transistors. Another advantage of down-scaling the transistor feature sizes is that it is possible to increase the (on chip) integration density.

Today’s experimental CMOS transistors have already been down-scaled to gate length values of 50-70 nm and SiO2 oxide thickness values of 1.2-1.5 nm

[4]. Due to these small dimensions, tunnelling of electrons through the insula-tor becomes possible. This tunnel current will become higher with respect to the wanted transistor currents iD by further down-scaling the CMOS

transis-tor feature sizes. The oxide thickness d should always be larger than 10 nm, in order to have an acceptable tunnel-current. Note that the tunnel current scales exponentially with the oxide thickness d. Transistors with high k ma-terial insulators allow a thicker insulator thickness d for the same transistor specifications, and therefore forms a hot research topic at the moment. How-ever, a fundamental limit in down-scaling CMOS transistors, even with high

k insulator transistors, is coming in sight and the search for ’work around’

solutions or other devices is therefore highly encouraged.

This thesis is focussed on single-electron tunnelling (SET) devices. Tunnelling of electrons through thin insulators in SET devices is desired and is used for signal processing. This is in contrast to CMOS technology, where the tunnel currents enlarge both the static and the dynamic currents through the tran-sistors. The tunnel current lowers the performance of the CMOS transistors and are therefore an unwanted property.

SET devices are capable of operating in the single-electron transport (SET) regime. In this regime, only a few electrons are needed for signal processing and only during dynamic transitions. In case the signal is static, these devices are in Coulomb blockade [5] and therefore the dissipated energy equals zero. This is similar to the behavior of CMOS circuits, however, for SET circuits,

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1.1 SET junction, tunnelling & Coulomb blockade 3

the currents are scaled down to a countable number of electrons.

The single-electron tunnelling devices might be scaled down almost to the molecular level. SET devices can be faster and consume less power than com-parable devices implemented in CMOS or bipolar technologies. Therefore the SET devices look very promising and form for that reason the topic of this thesis.

1.1 SET junction, tunnelling & Coulomb blockade

The SET junction consists of two conductors with a very thin insulator in be-tween. This structure therefore could behave like a normal capacitor when no tunnelling occurs. However, due to the extremely thin insulator d, tunnelling of electrons through the insulator becomes possible.

The tunnel process of electrons is described in the theory of quantum me-chanics [6]. The effect of tunnelling is defined as: ”the finite possibility of finding an electron on the other side of the insulating barrier”. According to this theory, the insulator thickness d, is calculated to be smaller than 10 nm in order to have an acceptable chance on single-electron tunnelling [7]. A typical value for the insulator thickness d is 7 nm.

The typical feature sizes of the SET devices are in the nanometer range, there-fore SET devices belong to the group of nano-electronics. CMOS and bipolar devices use to have typical feature sizes in the micrometer range and there-fore belonged to the group of micro-electronics, however, since gate lengths of NMOS transistors already reached values of 30 nm [3] and less, MOS devices also participate in the group of nano-electronics.

The tunnelling effect in a metallic SET junction was measured in the 1960’s. In 1969 [8], measurement results are given of an experiment with an nickel/lead SET junction (Ni− NiO − Pb) connected to a voltage source. From these mea-surement results, the relation between the current through the SET junction

i, versus the voltage level v across it are obtained. In the low voltage range,

the relation between these two quantities i and v is almost linear and is there-fore called the ’tunnel resistance’ RT. (RT = v_i). In this ’linear’ region, the

tunnel events are random and independent of each other and the distribution function for the subsequent tunnel events can therefore can be described with a Poisson distribution function [9]. This is described in section 6.1. The

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tun-4 Introduction

nel resistance RT is only used as a circuit parameter when the SET junction

conducts a current.

When a SET circuit is in Coulomb blockade, the parameter RTbecomes

mean-ingless, because there can be a voltage across a junction, without having any current flowing through it. For this case, only the capacitance value CTJ is a

valid parameter. The capacitance value CTJ is used as second parameter for

describing and modelling the SET junction in the literature. The value of CTJ

determines the minimum voltage difference across the SET junction, in order to expect a tunnel event. This required voltage difference to have tunnelling is called the critical voltage of that SET junction. How to obtain the value for the critical voltage is described in detail in chapter 3.

The effect of the Coulomb blockade was first measured in the mid-eighties, by Likharev [5] (1986). The first experiment on a SET structure containing an island was then performed. The existence of an island is a necessary con-dition in order to make the Coulomb blockade possible.

The charge residing on this island can be influenced with a (gate) capacitor connected to it. This SET sub-circuit is called the single-electron tunnelling transistor (SETT). With this SET circuit it is possible to have amplification in the voltage domain. Using this transistor, many circuits were proposed where the NMOS and PMOS transistors in existing CMOS circuits were just sub-stituted by these SET transistors, for example [10, 11]. In the case of digital signal processing, the SETT is not very suitable, since it is consuming more power and it is slower with respect to digital SET logic circuits operating in the single-electron transport mode. The SETT based circuits are also not op-timal with respect to compactness and efficiency of the design. Therefore it is important to understand the (inherent) working principle of the SET devices in order to make fast, compact and low power SET logic circuits.

In this thesis much emphasis is put on how to properly use, design and simu-late SET circuits, in order to get compact, extremely low power SET circuits using the least amount of circuit components.

When a SET device is designed properly, it can operate faster than a compa-rable CMOS device, using less power. In section 1.2, a comparison between a CMOS inverter and a SET inverter is given. Comparison is made using the specifications from the ITRS Road-map for Nano-electronics 2003 [12].

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1.2 SET technology versus CMOS technology 5

1.2 SET technology versus CMOS technology

In the literature, SET technology is often compared to state of the art CMOS technology. In order to compare the two technologies, the following bench-marks can be used:

• Power consumption • Speed

• Voltage gain

• Maximum operation temperature • Fan-in and Fan-out

The Technology Road-map for Nano-electronics 2003 [12](page 79) predicts for the year 2012 that SET logic circuits will have a circuit speed of 10 MHz at 77 K, while CMOS logic circuits will have reached a circuit speed of 10 GHz at 400 K. This prediction means that SET technology likely will never be able to perform faster logic tasks than its CMOS counterpart.

However, this prediction is based on SET circuits which are operating in the high current (HC) regime (like in the case of a SET transistor). In this HC regime, a large number of electrons are needed to charge and discharge the load capacitance of a SET circuit. Numerous examples of SET circuits op-erating in the HC regime can be found in literature [11, 13]. The maximal switching speed for these SET circuits is determined by its RC time constant, consisting of the tunnel resistance RTand the SET junction capacitance value CTJ. A practical value for the tunnel resistance RT is 100 kΩ and a practical

value for the junction capacitance value CTJ is 100 aF. This means that the

RC time constant equals 10 ps.

When a SET circuit is operating in the single-electron transport (SET) regime, where the information is carried by one or just a few electrons, the circuit is able to perform to its full advantage. A SET circuit operating in the SET regime can have the smallest available transition times 10−15 _{s (explained in} section 3.3), the lowest possible power consumption (working with just a few electrons at µV or mV voltage ranges) and it can have the highest achiev-able voltage gain. In section 4.6, an example of a SET circuit, operating at switching times in the order of 10−15_{s is discussed and simulated using SPICE.}

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6 Introduction

The maximum operation temperature for proper operation and the input, and output capacitance do not significantly differ between the two regimes. This is explained in chapter 2.

In table 1.1, a few important properties for SET circuits operating in the high current (HC) regime and operating in the the single-electron transport (SET) regime are compared to each other. Where RBC stands for the random background charge fluctuation in SET circuits, which is explained in chapter 2.

HC regime SET regime

Model parameters RT, CTJ CTJ

Information represented by currents one or a few electrons

Analog logic possible yes yes

Digital logic possible yes yes

Sensitivity to RBC fluctuations γ γ

Maximum operation temperature Tmax ∝ _C_{ef f}1 Tmax ∝ _C_{ef f}1 Minimal switching time 10−11_s ₁₀−15 _s

Maximum voltage gain low high

Table 1.1: Comparison between SET circuits operating in the high current regime and SET circuits operating in the single-electron transport regime. From table 1.1 it is clear that investigating SET circuits that are operat-ing in the soperat-ingle-electron transport (SET) regime are more promisoperat-ing than SET circuits operating with (high) currents. The SPICE model for the sin-gle SET junction is therefore optimized for sinsin-gle-electron transport behavior only. However, it is possible to simulate SET circuits operating in the HC regime, but special measures have to be taken in order to get accurate results. This is explained in detail in section 3.8.

When a SET circuit operates in the single-electron transport regime, it is even possible to outerperform the CMOS counterpart on both the properties power consumption and speed. In CMOS technology, the conducting state is obtained by a thin inversion layer, which is dense enough to conduct a current between the source and the drain [1](page 31). To obtain this inversion, a voltage in the hundred mV range has to be applied, depending on the process properties and the type of semiconductor used [14].

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1.3 Equivalent model for a single SET junction 7

Compared to a SET circuit operating in the SET regime, where the infor-mation is carried by one or just a few electrons and a supply voltage in the hundred µV range can be applied [15], it is clear that CMOS technology can-not compete with these power consumption properties.

A SET circuit operating in the SET regime can even obtain a switching time in the order of 10−15 _{s (explained in section 3.3), while in CMOS technology} the switching speeds are predicted to be on the order of 10−10 _{s by the year} 2012 [12] and is probably never able to compete to the switching speed values of SET technology. In table 1.2, a summary between a digital SET circuit operating in the SET regime and a digital CMOS circuit is printed:

CMOS circuit SET circuit Maximal switching speed 10−10 _s ₁₀−15 _s

Supply voltage range 100 mV 100 µV

Current range nA a few electrons

RBC sensitivity none γ

Maximum voltage gain high high

Maximum operation temperature > 300 ◦_C[16] _{difficult at 300 K} Table 1.2: A comparison between digital SET circuits operating in the single-electron transport regime and digital CMOS circuits.

1.3 Equivalent model for a single SET junction

An equivalent circuit model has been developed for a single SET junction, which is the first model based on voltages and currents to the author’s knowl-edge. This model is called the impulse circuit model for a single SET junction [17]. The model is suitable for both circuit analysis and design purposes. The challenge of implementing the impulse circuit model direct into the SPICE and Spectre [18] simulator is the subject of this thesis. A SET junction model in such an environment has many advantages. First, a good graphical user interface (GUI) and a good arithmetic kernel are already available. Secondly, it is possible to couple SET circuits to conventional electronic circuits and simulate them together. Thirdly, the existing set of computer aided design (CAD) tools and design environment used for very large integration (VLSI) CMOS can be used for nanoelectronic circuit design.

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8 Introduction

Measurement results on the SET circuits are used for validation of the im-pulse circuit model and the SPICE model and is the starting point of this thesis.

Basically, the impulse circuit model consists of a lumped capacitor with a delta-function current source placed in parallel to it, see Fig. 1.1. When the voltage across the SET junction exceeds a certain critical voltage, the current source is triggered and a charge of one electron, which equals the elementary charge e, is effectively transferred between the nodes of the SET junction, i.e.,

it = eδ(t). When the voltage across the junction is below the so called ’crit-ical voltage level’, the value of the current source equals zero and the model behaves like a true capacitor.

C

_TJ

i

_t (1) (2)

= e

δ

(t)

+

-Figure 1.1: The impulse circuit model of a single SET junction, consisting of lumped circuit elements.

In the impulse model, the critical voltage is defined as the maximum allowed voltage across the junction just to remain in the Coulomb blockade region. This is explained in detail in chapter 2.

The simulator can be used to find the value of the critical voltage, or it can be calculated by hand. The impulse circuit model is implemented in SPICE using standard components from the SPICE library. However, the delta pulse function is not available in the user environment of SPICE. Therefore different pulse shapes are used in order to transfer the elementary charge between the nodes of the junction. These functions mimic the delta function. Since every pulse shape in SPICE has a finite width, a certain ’tunnelling time’ is enforced. This tunnelling time is the total time needed for an electron to tunnel, includ-ing the time for the circuit to settle again into a new equilibrium state. (The external sources are assumed to be static at that moment). The introduction of the tunnel time is unavoidable, but it is nevertheless a practical parameter since the existence of a tunnel time is indicated by measurements [19].

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1.4 Existing SET circuit simulation programs 9

The shape of the pulse is an important aspect with respect to the numerical accuracy in SPICE. In section 3.8.4, different pulse shapes and their relation-ship to accuracy are discussed in detail.

Another important aspect of the proposed impulse circuit model is that it models a single SET junction [17], making it possible to simulate any arbi-trary SET circuit as an ensemble of single SET junctions.

1.4 Existing SET circuit simulation programs

The SET circuit simulators and models discussed in this section are all based on the orthodox theory (OT) of single electronics [19]. This theory describes the phenomena of single-electron tunnelling in terms of global free electro-static energy formulas. Therefore, it is only possible to make a SPICE model for a complete (global) SET circuit. This implies that for every change in the (SET) circuit topology, a new SPICE model has to be developed, which is of course highly inconvenient.

A few examples of SPICE models, based on the OT of single electronics, which are (only) able to simulate a SET transistor circuit, are given in [20, 21, 22]. However, all of these SPICE models are incapable of simulating a single SET junction or an arbitrary SET circuit including resistors. A practical example of a SET circuit that is not composed of SET transistors is the electron pump circuit [23]. For all SPICE models mentioned, a new model has to be made for this electron pump.

Also, various non-SPICE based SET circuit simulation programs exist. A major drawback of these simulators is that there is no opportunity to couple SET circuits to conventional electronic circuits and simulate them together. An example showing the importance of the combination of SET circuits and conventional electronic circuit components is given in section 4.1 and 4.7. A number of SET simulation programs, all based on the OT of single electronics is discussed in brief in this section.

A Single Electron Device and Circuit Simulator (SIMON) is a simulator for single-electron tunnel devices and circuits developed by C. Wasshuber [24]. It has a user friendly graphical user interface (GUI) and it can calculate transient and stability behavior of SET circuits using the Monte Carlo method. It is

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10 Introduction

also possible to simulate a SET circuit combining the Monte Carlo method with a direct solution of the stationary Master Equation [24], in case the SET circuit has rare and frequent tunnel events occurring at the same time. A Monte-Carlo Single Electronics Simulator (MOSES) is developed by R. H. Chen [25]. The simulation results of SET circuits without resistive elements are identical to Simon’s simulation output.

Seneca is a simulation program which is suitable to calculate error rates due to cotunneling in single-electron circuits containing several SET junctions, de-veloped by L.R.C. Fonseca [26].

The Single-Electron Tunnelling Transistor (SETTrans) simulator is a simu-lation program that is able to handle the SET transistor only. With this simulation program, it is possible calculate and plot an i-v curve and the derivative of the i-v curve: _dvdi, as well as the derivative of the i-q curve: di_dq of the SET transistor. This program is developed by A. N. Korotkov [27]. The programs and models described above are not able to simulate resis-tors properly, because resistive behavior in general is not well modelled in the OT of single electronics. The OT of single electronics can only predict the correct behavior for a SET junction in a low ohmic environment, or in a high-ohmic environment. The distinguishing factor between low - or high-high-ohmic environments is the ’quantum resistance’, RK [19]. The value of RK is given

by: RK= _eh2, where h is Planck’s constant and e equals the elementary charge.

The OT of single electronics can not predict the behavior of a SET junction if e.g., the impedance levels in surrounding circuit are in the order of RK.

A SET junction model which is not based on the OT of single electronics is the SPICE model for a single SET junction, which is described in this thesis. This model is based on the theory of the impulse and extended hot-electron models [28], which are described in chapter 3. The basic SPICE model for a single SET junction was first published in [29]. It is the only model available to simulate a single SET junction or any arbitrary SET circuit in a SPICE like environment.

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1.5 The main problems in SET technology 11

1.5 The main problems in SET technology

In this section, the main problems facing commercial SET technology are briefly discussed. A detailed explanation of these topics is given in section 2.2.

• Low operating temperature • Fabrication problems • Measuring problems • Interconnecting problems

• Random background charge (RBC) fluctuations

The operation temperature T for proper operation of a SET circuit scales inverse proportional to the capacitance values CTJ’s and C’s of the circuit. In

equation 1.2, this is given mathematically (which is proven in section 2.2.1).

T ∝ 1

C_TJeff (1.2)

Therefore, the problem of the making the operation temperature T of SET circuits as high as possible is principally the same problem as making the ca-pacitance values of SET junctions, and other capacitors in the circuit, as small as possible (while the insulation thickness d must be kept constant (approxi-mately 7 nm) in order to obtain proper tunnelling).

At the ISSCC 2003 [30], an example of a voltage biased SET transistor is given. The junction capacitances are in the order of 100 zF (zepto = 10−21_). Oper-ation of the SET transistor was measured successfully at room-temperature. It is still difficult to fabricate small capacitance SET junctions with a rea-sonable accuracy and yield. Generally, the smaller the capacitance value, the lower the accuracy will be. In this thesis no solutions for this problem are given, because this problem is on the technological level and will probably be solved within 10 years. The main problem is the lack of a small lithographical resolution in order to obtain these small devices. Note that in 2002 it is al-ready possible to successfully fabricate junctions with 100 zF values in small numbers [30].

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12 Introduction

Measuring problems occur when the voltage in a SET circuit represents the signal of interest. It is not possible to measure the voltage directly across a SET junction, since the capacitance values of the SET junctions are extremely small. When the SET junction is loaded directly with the input capacitance value of the test equipment, the circuit will not function properly anymore. State of the art measuring equipment in 2003 was the device characterization system SCS4200 of Keithley [31]. This device has an current resolution of 100 aA, a voltage resolution of 10 µV and an input impedance of 100 GΩ and 1 pF. However, additional SET circuits can be used as an interface between the measuring device and the voltage to be measured (across a SET junction). A few examples are given in section 2.2. Another way to measure a voltage indirectly is to use a capacitive voltage divider to avoid loading the SET junc-tion. A simulation result of this solution is shown in section 4.7. However, the signal is attenuated by the same factor that the load capacitance is decreased and therefore (on-chip) signal amplification is needed. Note that measuring a small current through a SET circuit does not cause any difficulties in measur-ing.

The interconnecting problems arise when the complexity of the SET circuits increases. The main problem is that the interconnecting conductors some-times cannot be short enough in order to neglect their induced capacitance value (with respect to ground). This problem is increased if the desired op-erating temperature T is increased. Then the capacitance values of the SET junctions and capacitors in the SET circuit have to be extremely small. (i.e., zF capacitance values for room temperature operation). This means that the interconnecting wire capacitance values have to be much smaller, which can be difficult to realize. The resistance of the conductors are not expected to form a problem for SET circuits.

The RBC fluctuation problem is not solved at the device-level yet. Proper shielding, using a smooth surface (on the atomic level) and a clean substrate (where the number of impurities less than 1 part per million) and using special equipment do help reducing the RBC fluctuations problem, however, they do not avoid them. Therefore, it is important to develop robust SET electronic circuits that are able to cope with this kind of disturbance. One possible way to create robust circuits with these junctions is to use redundancy at levels higher than the device level [32]. A neural network is one possible way to generate this redundancy; this is described chapter 5 of this thesis. In section

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1.6 Neural networks and SET technology 13

1.6, a brief introduction into neural networks is given.

1.6 Neural networks and SET technology

An artificial neural network is composed of a (preferably large) number of sim-ilar and interconnected building blocks. Each building block consists of a set of mostly non-linear and adaptable functions. The network operates similarly to the way we believe the biological (human) brain works.

Rosenblatt [33] described the biological inspired artificial neural network by modelling the neuron and multiple synapses in one model, which he called the perceptron model. The perceptron is used as a starting point for developing the artificial neural network in this thesis. A detailed discussion on the neural perceptron is given in chapter 5.

A neural network is a suitable architecture for SET devices which is able to cope for the unwanted errors which are introduced by the floating islands. In Fig. 1.2 a graphical representation showing the mutual benefits for the combination of neural networks and SET devices is shown.

SET devices Neural processing elements

Small in physical dimensions Extremely low power

Generates random errors A large number of processing elements are needed Redundancy at a higher abstraction level; possibility

to cope for random errors

Figure 1.2: Graphical representation showing the mutual benefits arising from the combination of neural networks and SET devices.

The combination of neural networks and SET technology has two advantages. First, a powerful neural network requires a large number of neural nodes. This implies each neuron has to be small in dimensions due to restricted available space. Also, the power dissipation of each neural node has to be extremely low in order to have an acceptable overall power-dissipation [34] (and heat

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14 Introduction

dissipation). In these aspects, SET devices are very suitable in neural net-works, because they are extremely small and can process information using only a few electrons. Secondly, capacitively coupled SET devices introduce errors like RBC fluctuations.

Some basic background information on neural networks is given in chapter 5 of this thesis. In section 5.4, three complete perceptrons designed using SET devices are compared to each other. A SPICE simulation result of an artificial complete (new) perceptron is shown and discussed.

1.7 Thesis objectives

The main objectives of this thesis are:

(1) To show how to design SET circuits from an electronic point of view with respect to low power properties, speed and circuit complexity. For exam-ple, instead of substituting SET transistors for MOS transistors in standard CMOS circuits, to redesign SET circuits utilizing the single-electron transport features of the SET junctions, in order to obtain SET circuits which can have better performance specifications than their CMOS counterparts.

(2) To develop a SPICE model that is able to simulate a single SET junction. There is no SPICE model available that can simulate hybrid circuits con-sisting of arbitrary SET circuits in combination with conventional electronic components. The model presented in this thesis is validated qualitatively with numerous measurement results found in literature. These measurements and there corresponding simulation results are shown and discussed in section 4.1. (3) To introduce and show useful tools that can help designing SET circuits. Note that existing electronic models, like the hybrid-π small signal transistor model and frequency models are not applicable for SET circuits. One of the tools that can be useful for designing SET circuits is a state diagram simu-lation tool. This simusimu-lation tool helps the designer to get insight in how to choose proper external source values in order to obtain the desired operation function for any given SET circuit for a certain parameter set.

(4) To illustrate that the combination of neural networks and SET technology have multiple mutual benefits. This proposition is strengthened using a few examples and simulation results.

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1.8 Thesis outline 15

1.8 Thesis outline

This thesis is divided into four parts, namely:

• The introduction into SET circuit design.

• The theoretical description and implementation of the SPICE model. • Discussion on SET circuits and corresponding simulation results and the

validation of the SPICE model.

• Neural networks and SET devices

The introduction to SET circuit design, described in chapter 1, is meant to give the reader an impression of the world of SET technology today (2004). A few state of the art examples are discussed in brief, showing what might be feasible and what to expect in the near future. A number of problems SET technology is facing are discussed and for some problems a possible solution is given in this thesis. In chapter 2, an introduction in the working principles of SET devices is described. This knowledge is needed in order to understand the working principles of the SPICE model.

In the second part of this thesis, the underlying theory of the SPICE model is described (in chapter 3). This theory is divided in two parts: the im-pulse circuit model for the single SET junction and the extended hot-electron model. In chapter 3, the SPICE model, its working principle and a number of work-around solutions in order to operate the model properly in SPICE are described in detail. In chapter 6, extensions to the SPICE model are discussed in order to simulate temperature dependency and the stochastic behavior in SET circuits.

In the third part of this thesis, a number of important known and new SET circuits are analyzed. Analytical descriptions and simulation results are shown for all these circuits. A special group form the SET circuits which are actually measured. Experimental results from these measurements is used for valida-tion purposes of the SPICE model and are shown in chapter 4.

The fourth part of this thesis consists of an introduction in artificial neu-ral networks, which is topic of chapter 5. This discussion is needed in order to interpret the simulation results on neural networks given in section 5.8.

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16 REFERENCES

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engi-neering, Dover Publications Inc., New York, 1991.

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[8] I. Giaever, “Metal-Insulator-Metal Tunneling,” in Tunneling Phenomena

in Solids, pp. 19–30. Plenum Press, Edited by E. Burstein and Lundqvist,

New York, 1969.

[9] A. Leon-Garcia, Probability and Random Processes for Electrical

Engi-neering, Addison-Wesley, ISBN: 0-201-50037-X, May 1994.

[10] R.H. Chen, A.N. Korotkov, and K.K Likharev, “Single electron transistor logic,” Applied Physics Letters, vol. 68, no. 14, pp. 1954–1956, April 1996. [11] M.Y. Jeong et al., “Performance of single electron transistor logic com-posed of multi-gate single electron transistors,” Japanese journal of

ap-plied physics, vol. 36, no. 11, pp. 6706–6710, November 1997.

[12] J. De Boeck et al., ”Technology Roadmap for Nanoelectronics”, European Commission, http://www.cordis.lu/esprit/src/melari.htm, 2003.

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REFERENCES 17

[13] M.J. Goossens, J.H. Ritskes, C.J.M. Verhoeven, and A.H.M. van Roer-mund, “Neural networks with periodic single-electron tunneling transis-tors,” in ECCTD’97, Budapest, Hungary, pp. 936–941.

[14] N.Donckers, C.Dualibe, and M. Verleysen, “A current-mode CMOS loser-take-all with minimum function for neural computations,” ISCAS, 2000. [15] C.P. Heij, P. Hadley, and J.E. Mooij, “A single-electron inverter,” Applied

Physics Letters, vol. 78, no. 8, February 2001.

[16] P.C. de Jong, Smart Sensor Systems for High-Temperature Applications, Phd thesis, TU Delft, Mekelweg 4, November 1998.

[17] J. Hoekstra, R.H. Klunder, R. van de Haar, E. Rouw, and P.Chand, “Circuit design with metallic single-electron tunneling junctions,” in

ES-SCIRC 2002, Firenze, Italy, September 2002, pp. 671–674.

[18] K.S. Kundert, The Designer’s Guide to SPICE and SPECTRE, Kluwer Acedemic Publishers, 3rd edition, 1998.

[19] Edited by H. Grabert and M.H. Devoret, Single charge tunneling Coulomb

blockade Phenomena in Nanostructures, vol. 294 of NATO ASI series B,

Plenum Press, New York, physics edition, 1992.

[20] Y.S. Yu, J.H. Oh, S.W. Hwang, and D. Ahn, “An equivalent circuit approach for the single electron transistor model for efficient circuit sim-ulation by SPICE,” Electronics Letters, vol. 38, pp. 850–852, 2002. [21] S. Amakawa, H. Majima, H. Fukui, M. Fujishima, and K. Hoh, “Single

electron circuit simulation,” IEICE Transactions on Electronics, vol. E81-C, no. 1, pp. 21–29, January 1998.

[22] G. Lientschnig, I. Weymann, and P. Hadley, “Simulating hybrid circuits of single-electron transistors and field-effect transistors,” Japanese Journal

of Applied Physics, 2003.

[23] A.B. Zorin, S.V. Lotkhov, H. Zangerle, and J. Niemeyer, “Coulomb block-ade and cotunneling in single electron circuits with on-chip resistors: to-wards implementation of the R-pump,” Journal of Applied Physics, vol. 88, no. 5, pp. 2665 – 2670, 2000.

[24] C. Wasshuber, H. Kosina, and S. Selberherr, “Simon - a Simulator for single electron tunnel devices and circuits,” IEEE Transactions on

Com-puter Aided Design of Integrated Circuits and Systems, vol. 16, no. 9, pp.

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18 REFERENCES

[25] A.N. Korotkov, R.H. Chen, and K.K. Likharev, “Possible performance of capacitively coupled single electron transistors in digital circuits,” Journal

of Applied Physics, vol. 78, no. 4, pp. 2520–2530, August 1995.

[26] L.R.C. Fonseca, A.N. Korotkov, K.K. Likharev, and A.A. Odintsov, “A numerical study of the dynamics and statistics of single electron systems,”

Journal of Applied Physics, vol. 78, no. 5, pp. 3238–3251, September 1995.

[27] K.K. Likharev, “Single-electron devices and their applications,” in

Pro-ceedings of the IEEE, April 1999, vol. 87, pp. 606–632.

[28] J. Hoekstra, “Single-electron tunnelling circuits,” in Fundamentals of

Na-noelectronics S.Buegel , M. Luysberg, K. Urban, R. Waser (Eds.), vol. 14

of Schriften des Forschumgszentrums Juelich Reihe Materie und

Mate-rial/Matter and Materials, chapter D - Concepts for Nanoelectronic

De-vices, pp. D7.1–D7.16. Forschungszentrums Juelich, 2003.

[29] R. van de Haar, R.H. Klunder, and J. Hoekstra, “SPICE model for the single electron tunnel junction,” in ICECS, Malta, September 2001, vol. 3, pp. 1445–1448, ISBN: 0-7803-7058-9.

[30] K. Uchida, Junji Koga, Ryuji Ohba, and Arika Toriumi, “Programmable single-electron transistor logic for low-power intelligent Si LSI,” in IEEE

international Solid State Circuits Conference. ISSCC, 2002, pp. 206–207.

[31] Keithley, “Enhanced model 4200-SCS for DC characterization and stress-measure and reliability testing,” www.keithley.com.

[32] A.H.M. van Roermund and J. Hoekstra, “Design philosophy for nano-electronic systems, from SETs to neural nets,” International Journal of

Circuit Theory and Applications, vol. 28, no. 6, pp. 563–584, 2000.

[33] F. Rosenblatt, Principles of Neurodynamics: Perceptrons and the Theory

of Brain Mechanisms, Spartan books, New York, 1962.

[34] J. Hoekstra, J. Camargo da Costa, M.J. Goossens, C.J.M. Verhoeven, and A.H.M. van Roermund, “The application of neural networks for nanoelectronic circuits,” NEURAP, March 1998.

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Chapter 2

The SET junction

A metallic SET junction consists of two conductors with a very thin insulator in between. In Fig. 2.1 a sketch of a single SET junction is shown. Aluminum is used often as a metal conductor in practical SET junctions, because it is available in many standard IC processes. Aluminum oxide is then grown on aluminum. The speed aluminum oxide grows is well under control, and there-fore the insulation thickness is also well defined. The chemical composition for the aluminum SET junction is: Al − Al2O3− Al.

d w h (a) (b) TJ Al Al2O3 Al

Figure 2.1: (a) Sketch of a SET junction. (b) The schematic symbol. The metallic SET junction has been investigated and measured in the 1960’s, by i.e., Giaever [1]. From these measurement results, a new model is developed using two model parameters. These model parameters are:

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20 The SET junction

• the tunnel capacitor CTJ

• the tunnel resistor RT

The first model parameter is the tunnel capacitor CTJ. For an aluminum

SET junction with a capacitance value CTJ of 1 aF, the physical dimensions

can be calculated according to the capacitance formula shown in equation 2.1 (fringing effects are not taken into account).

C = ²0· k · A

d (2.1)

The area A is equal to w · h. Typical dimensions are: d=7 nm, w=10 nm and h=8 nm (for Al2O3 the k factor is approximately 9.8 [2]).

The device description for a SET junction is the same as for a normal ca-pacitor if there is no conduction current due to tunnelling. However, due to the thin insulator (d on the order of nm), tunnelling of electrons through the insulator is possible.

In the theory of quantum mechanics the tunnel phenomenon is well described. It is stated that in order to have a significant probability for electrons to tunnel through an insulator, the insulator thickness has to be smaller than 10 nm [3]. Tunnelling is defined as the possibility for an electron to go through a poten-tial barrier, even if its kinetic energy is less than the height of the potenpoten-tial barrier [4].

Note that only on the aspect of tunnelling, the tunnel-junction differs from a true capacitor. So when no tunnelling occurs, the SET junction is a normal capacitor.

The second parameter specified for the SET junction in literature is the tun-nel resistance RT. This tunnel resistance RT is equal to the voltage across

the junction divided by the current through the junction. At low voltages, this value is approximately constant. In Fig. 2.2, a measurement result of a voltage excited Ni − NiO − Pb SET junction at a temperature of 4.2 K is shown. The measurement was performed in 1969 by Giaever [1]. The tunnel resistance RT is approximately linear from 0 to 100 mV. In the zoomed box

of Fig. 2.2, the tunnel resistance RT is extracted from the slopes, expressed

in equation 2.2. RT= v i = 0.02 V 0.1 mA = 200 Ω (2.2)

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21

This value for RT is very low for a SET junction, which indicates that the

insulator thickness d is relatively small (estimated value 2 nm).

0 0.2 0.4 0.6 0.8 1 -10 0 10 20 30 40

(a)

_(b)

i [mA] v [V]

i

TJ

v

+

R_T 0 0.1 0.02 R_T

Figure 2.2: (a) Voltage excited SET junction. (b) Measurement result of a voltage exited N_i− N_iO − P_b SET junction @ 4.2 K.

In the linear region, the tunnel events are independent of each other and can be described by a Poisson distributed random variable [5]. This will be fur-ther explained. The tunnel resistance RT is only defined when a current is

flowing through the SET junction, which is defined as the high current (HC) regime in section 1.2. The tunnel resistance therefore only gives the relation between v and i for average values. The tunnel resistance has no meaning for single tunnel events or in the Coulomb blockade region. Note that the SPICE model for the single SET junction discussed in this thesis does not support the junction parameter RT. However, when stochastic behavior is added to

the SPICE model, then the tunnel resistance RT can also be modelled.

In this work, we are only interested in single-electron behavior and not in high current behavior. Therefore the tunnel resistance RT is not included in

the SPICE model. In table 1.1 of section 1.2, a few important properties for SET circuits operating in the high current (HC) regime and operating in the single-electron transport (SET) regime are compared to each other, strength-ening the motivation of not adding the tunnel resistance RT parameter into

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22 The SET junction

2.1 The benefits of using SET technology

The motivation to look at the metallic single-electron tunnelling junction as a promising nanoelectronic device candidate is for the following reasons:

• A new process technology is not required • Only two metal layers are required

• Circuits can be extremely low power by using a countable

number of electrons for signal processing

• Switching speeds in the order of 0.1 fs to 1 fs can be reached. • The devices are small in physical dimensions, making

extremely high integration densities on-chip possible

SET technology can be integrated into a standard CMOS IC process using alu-minum metal layers. It is also possible with other metals, however, alualu-minum is relatively mature. Aluminum oxide is used for the insulation in between the two metal layers.

The SET junction is a two terminal device, and therefore only two metal layers are needed for circuits in a 2D surface. If 3D circuits are needed, more metal layers are needed in order to obtain a higher integration density. SET circuits that operate in the single-electron transport regime can pro-cess information by only a countable number of electrons. The electrons are optimally used when one electron represents one bit in digital signal processing. SET circuits operating in the single-electron transport regime can obtain switching speeds in the order of 0.1 fs to 1 fs, depending on the biasing of the circuit. This will be explained in chapter 3.

SET devices are extremely small in physical dimensions. The origin can be found by quantum mechanics. The typical insulation distance between the two conductors for independent tunnelling is 7 nm. In order to obtain a small capacitance value for the junction (atto-Farad range), the height and width of the junction also have to in the nm range. A small capacitance value is needed to obtain a high operation temperature and signal to noise ratio. For example, sub-atto-Farad SET junctions are needed at room temperature.

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2.2 Problems in SET technology 23

However, before SET junctions can be used on a large scale for both digi-tal and analog signal processing, a few problems have to be tackled. This is the topic of section 2.2.

2.2 Problems in SET technology

As mentioned in section 1.5, the main problems SET technology is still fac-ing are: the low operatfac-ing temperature, fabrication problems, interconnection problems, the random background charge fluctuation problems and the mea-surement problems. These problems will be discussed in the next subsequent sections.

2.2.1 Low operating temperature

As mentioned in section 1.5, the operating temperature of SET circuits in-creases as the capacitance of SET junctions dein-creases, since the operating temperature T scales in proportion to the effective capacitance of the SET junction between two nodes, 1/C_TJeff, thus

T ∝ 1

C_TJeff (2.3)

Note that the insulation thickness d should be constant (in the order of 7 nm). If d is taken smaller than 7 nm, then the sequential tunnel events will not be independent anymore, which means that the tunnel process can not be de-scribed according to Poisson’s distribution (explained in chapter 3). If d is taken larger than 7 nm, then the probability on a tunnel event drops exponen-tially with respect to the width, which results in unrealistic long wait times before sequential tunnel events occur, resulting in unusable circuits.

In SET circuits, there is one dominant type of noise and that is the ther-mal noise. The average therther-mal energy in this noise component is given by the relation of Boltzmann. Boltzmann’s constant kBrelates the average energy

of a molecule to its absolute temperature. Using this definition, the relation between the average thermal energy in a SET circuit and its absolute temper-ature, is given in formula 2.4.

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24 The SET junction

In order to show that equation 2.3 holds, the SET circuit, shown in Fig. 2.3 is examined. In this figure, the circuit diagram of a current source connected to a SET junction is shown.

i_DC TJ

a

1 aF

Figure 2.3: Circuit diagram of a current source connected to a SET junction. The signal energy Esignal in the SET junction of Fig. 2.3, scales proportional to 1/CTJ. The derivation is given by equations 2.5, 2.6 and 2.7. The

follow-ing equations are only valid for linear cases, this means, the are in Coulomb blockade. An electron will tunnel through the SET junction when the voltage has reached the value of vcr_{. At this moment, the electron can tunnel, and} the corresponding energy value is called the signal energy Esignal.

vcr = e

2 · CTJ

(2.5)

Esignal = 1₂ CTJ· (vcr)2 (2.6)

Combining equations 2.5 and 2.6 gives:

E_signal= e2 8 CTJ

(2.7)

If the ratio of Esignal/Eth is kept constant, the temperature T scales propor-tional to 1/CTJ. This is expressed as:

E_signal Ethermal = e2 8 · CTJ· kB· T = α => T = 1 CTJ · e 2 α · kB· 8 (2.8) Where α is a constant. Since kB, e2 and 8 are also constants, equation 2.8

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Equation 2.3 holds in the general case [6]. The signal energy of equation 2.7, is in the literature often referred to as the Coulomb energy [6].

The maximum allowable operating temperature for an arbitrary SET circuit depends not only on the ratio between the energy given by the thermal noise with respect to the energy given by the signal in that SET junction, it also depends on the SET circuit itself. For example, when a SET junction is biased close to tunnelling, only a small amount of thermal energy is needed to let the SET junction tunnel. This is true for a SET junction operating in the single-electron transport (SET) regime, as well as for operation in the high current (HC) regime, because in both cases the tunnel criteria for the junction must be met before it is able to tunnel.

In chapter 6 an overview of practical environment temperatures and their related capacitance values with respect to their signal energy Esignal for SET junctions is given.

Note that the critical voltage for a SET junction is also independent of the operating regime (SET of HC regime). This means that if the SET junction is in Coulomb blockade, first the voltage difference across it has to be larger than vcr before tunnelling can occur.

2.2.2 Fabrication problems: accuracy aspects

SET junctions are difficult to fabricate. The difficult part is to create a SET junction with a small capacitance value C, with a reasonable accuracy and fabrication repeatability. This is predominantly caused by a coarse minimal fabrication step size of the aluminum in the lateral direction. This step size has to be in the nm regime. An example of physically realistic dimensions of a SET junction is given in (the caption) of Fig. 2.1. The insulator thickness d is made in the nm regime. However, this is not a dominant fabrication problem, because it is well known how fast, for example, a layer of 7 nm Al2O3 is grown

on top of Al. Therefore, the insulator thickness d is well under control and the lateral step size ρ is not. In Fig. 2.4 this problem for the minimal step size is made visible for one lateral direction. In practice electron beam lithography is used to obtain the small structures in the lateral direction on the nanometer scale.

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26 The SET junction

d

ρρρρ

Figure 2.4: Fabrication accuracy problems appear in the lateral dimensions of the aluminum layer. The insulator thickness d is well defined.

In this thesis no solutions for this problem are given, because this problem will probably be solved by technology scaling within 10 years. For example, in 2002 it was already possible to fabricate junctions with 100 zF values in small numbers [7]. In order to fabricate a large number of accurate (small) SET junctions, the fabrication techniques have to be improved in order to obtain accurate and repeatable small feature sizes of the devices.

2.2.3 Interconnecting problems

SET (sub)circuits are connected to each other by means of a metal conductors. These conductors have a capacitive component to the substrate and to other metal conductors and metal planes in the chip. The value of this parasitic capacitive component should be much smaller than the capacitance values of the SET junctions in the circuit in order to obtain the same functionality in case of ideal interconnects.

Since the signal to noise ratio scales inverse proportionally with the capac-itance values of the circuit, it is important to keep these parasitic capacitors as low as possible, especially when operating temperatures higher than 1 K are required. Typical values for SET junctions in practical samples very from 100 zF to 100 aF (see section 4.1).

2.2.4 Random background charge fluctuations

The random background charge (RBC) fluctuation problem is not solved at the device-level yet, but there are several ways to deal with this type of dis-turbance. Four types are discussed in this thesis:

• Put the information in the amplitude or frequency component of the

signal.

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• Use redundancy on a higher system level in order to reduce the overall

error rate.

2.2.4.1 Put the information in the amplitude or frequency compo-nent of the signal

The first two proposed solutions seem useful to conquer the RBC fluctuation problem. However, in the case of a capacitively coupled SET circuit, the out-put voltage is always obtained from an island (by definition), this means that there exists a specific value for the RBC for the particular node, where no voltage signal is output to the SET circuit. In case the output signal is in the current domain, the problem remains the same since there will be a certain node (island), where due to a specific RBC disturbance the output (current) signal will be blocked. This is called a ’RBC nullifier’. This means both so-lutions (amplitude and frequency) will fail in this situation. When the RBC value is close to the nullifier value, the output signal is too small to process and the signal will be lost.

However, if an additional circuit component is added to the SET circuit, for example an electrical variable capacitor (like a very small vari-cap diode) in the atto-Farad range. Then SET circuits can be developed which are insensi-tive to RBC fluctuations. An example of such a SET circuit with a proposed variable capacitor is given in [8]. When the capacitor is variable, the signal can be amplified to a desired level in order to avoid signal loss. However, since this extremely small variable capacitor is not available, these solutions are not yet feasible.

2.2.4.2 Use compensation (circuits) to control the charge among the islands

The compensation technique is used many times in measurement setups. In many cases an extra capacitor to the island is created in order to tune away the initial island charges and RBC fluctuations that may appear among the particular island by means of external gate voltage sources. This means that every island needs its own compensation capacitor and external (gate) voltage source [9]. In low complexity SET circuits, the island charges could be exter-nally controlled in this way. However, in SET circuits with a large number of islands (e.g., a neural network) this (external) option to compensate for unwanted charges, is not feasible.

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28 The SET junction

It is also possible to develop an electronic circuit to compensate for the un-wanted island charges on chip, however, if this compensation circuit is made in SET technology it will suffer itself from RBC fluctuations. And if the com-pensation circuit is made in CMOS technology, the integration density and the low power properties of the SET circuits will be lost. This means compen-sation is not a viable option for SET circuits with a large number of (floating) islands.

2.2.4.3 Use redundancy on a higher system level

A possible way to overcome the RBC fluctuation problem in SET circuits is to add redundancy to the hardware. This solution does not try to eliminate the problem at the source (as in the case for the previous solutions), but accepts that a particular SET processing element produces a false output. However, more SET processing hardware is needed in order to compensate for the false output for a particular piece of hardware, and obtain the desired overall sys-tem functionality.

Redundancy can be applied in many different ways. A neural network is a possible way to generate redundancy. A neural network is a special kind of majority voting based processing system. A typical example of majority vot-ing is to build every processvot-ing element (with binary output) three times and let 2 (or 3) of the same outcomes be declared the valid outcome. In Fig. 2.5, a three input binary majority voting element and its truth-table are shown. Note that the voting element itself is assumed to be faultless.

a b c 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 (a) (b) F 0 0 0 0 1 1 1 1 a b c F α α α 2 >

Figure 2.5: (a) A three input binary majority voting element. (b) The corre-sponding truth-table for the case α = true.

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In a neural network, different forms of redundancy can be distinguished. The value of the redundancy depends not only on the quality of the neural process-ing elements, but it is also very dependent on the network topology. This will be discussed in chapter 5. The redundancy is applied to the network in order to obtain robust overall system functionality. The robustness can be used as a figure of merit or measure of quality of a neural network.

Robustness is defined as the allowable amount of faulty neural processing elements with respect to the total number of neural processing elements in the network, in order to remain a valid overall functionality.

Generally, it will hold that for higher robustness, more hardware must be added. Signal redundancy is not discussed, because this can be applied to any SET circuit and will therefore make no difference to the hardware reliability. ( In chapter 5, a way to measure the robustness of an artificial neural network is discussed).

Note that special shielding, a clean environment, special equipment and wiring should always be used in order to reduce the unwanted disturbances as much as possible. As mamma always said: prevention is better than cure. However, it is not possible to avoid the RBC fluctuations from occurring.

The sensitivity to RBC fluctuations γ is applied to both SET circuits op-erating in the high current regime as well as for the single-electron transport regime. This will become clear when a suitable model for island charges is introduced. In Fig. 2.6, a model for island charges is shown [10]. The model consists of a current source from ground towards the island where the RBC is stored.

In this figure, an arbitrary SET circuit where a RBC fluctuation on island (b) is modelled by a current source is shown. However, it does not necessarily mean that current sources are restricted to modelling RBC, any island charge can be modelled this way. The RBC on the island is modelled by the delta function δ(t) at t = 0. This means that when the circuit is taken under consid-eration at t = 0+_{, the island charge is already transferred by the current source.}

From this model in Fig. 2.6, it is clear that for an RBC fluctuation (or any island charge) on island b there is no difference between a SET circuit in high current regime and a SET circuit in the single-electron transport regime.

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30 The SET junction +

C

_gx

TJ

_n

TJ

_m

v

b

q

_RBC

.

δ

(t)

Figure 2.6: An arbitrary SET circuit where RBC fluctuation on island (b) is modelled by a current source.

2.2.5 Measurement problems

The output signal from a SET circuit can appear in one of the following two signal domains:

• The current domain • The voltage domain

When the output signal of a SET circuit is in the current domain, it is not a practical problem to measure this current. This is due to the fact that currents in SET circuits are always flowing through SET junction voltage source loops, meaning that the current through the loop can always be measured at the (ex-ternal) power supply terminals. This also implies that the input capacitance of the measuring device can be much higher than the capacitance values used for the SET circuit components, because when a current measuring device is in series with the voltage source the input capacitance value of the current meter is of no influence.

In Fig. 2.7 an example of a voltage biased SET transistor circuit is shown. In this case the measurement is independent of the (large) capacitance value of

C_cable. Note that the SET sample does not need any changes in order to make the current measurement possible, because the power supply terminals were already the external terminals.

Modern measuring instruments nowadays have an in input impedance of 10 GΩ in parallel to 1 pF, and a current resolution of 100 aA [11], which has enough resolution to perform measurements on these kind of SET circuits.

Simulation of single-electron tunnelling circuits using SPICE

Simulation of single-electron tunnelling

circuits using SPICE

Simulation of single-electron tunnelling

circuits using SPICE

Contents

Index of symbols

Chapter 1

Introduction

1.1

SET junction, tunnelling & Coulomb blockade

1.2

SET technology versus CMOS technology

1.3

Equivalent model for a single SET junction

C

i

= e

δ

(t)

1.4

Existing SET circuit simulation programs

1.5

The main problems in SET technology

1.6

Neural networks and SET technology

1.7

Thesis objectives

1.8

Thesis outline

References

Chapter 2

The SET junction

(a)

(b)

i

TJ

v

+

2.1

The benefits of using SET technology

2.2

Problems in SET technology

C

TJ

TJ

v

q

.

δ

_(b)