Material-Inversion Solid-Phase Epitaxy of p+ Si for Elevated Junctions Y. Civale, L. K. Nanver, H. Schellevis
Laboratory of Electronic Components Technology and Materials, DIMES, Delft University of Technology, Delft, The Netherlands
A solid-phase epitaxy (SPE) process that forms ultra-shallow abrupt aluminum p+-doped Si islands has been studied for deposition temperatures from 400 to 500 ºC. The growth process gives a very uniform composition of the p+ layer and an abrupt doping transition to the Si substrate. Low ohmic contacting and near-ideal diode characteristics are reliably obtained.
Introduction
For the continued down-scaling of CMOS technology, the formation of ultra-shallow abrupt junctions is an important issue [1]. Moreover, in BiCMOS technology, the processing of such junctions without inducing transient-enhanced diffusion (TED) of the bipolar device doping profiles is crucial for attaining high cut-off frequencies. Junction formation techniques that give some promise of meeting the requirements fall into the category of high-temperature ultra-short-time anneals (e.g. flash, laser annealing [2,3]) and low-temperature methods using epitaxy (e.g. SiGe elevated or refilled junctions [4], or solid-phase epitaxy for recrystallization of ultra-shallow implanted regions [5]). Recently, we presented a solid-phase epitaxy (SPE) process based on material inversion of an aluminum/amorphous-silicon (α-Si) stack that offers a new solution to ultra-shallow p-type junction formation [6]. It was shown that the size and high quality of the SPE c-Si island could be well controlled by the stack thickness and lateral dimensions at a processing temperature of 500 °C.
In this study, we demonstrate the controllability of the whole process when the junction dimensions are reduced to the sub-100 nm range. The influence of reducing the processing temperature to 400 °C is also investigated by the fabrication and electrical characterization of p+-n diodes, p+ emitters for bipolar junction transistors and p+ contacts. A very good diode quality is achieved, which is particularly interesting in view the fact that the processing temperature is so low that all transient-enhanced diffusion of dopants is avoided. Moreover, the SPE p+-island to n-substrate transition is shown to be ideally abrupt and practically defect free. In particular, it is remarkable that even for junction areas as small as 200 × 200 nm2, the diodes have very low ideality factors. This is in contrast to conventional selective CVD-epitaxy processes used for elevated source/drain formation for which it is usually necessary to create some form of extra perimeter doping in order to eliminate perimeter diode leakage.
SPE Si Island Formation and Analysis SPE Si Island Formation
substrate that are defined by optical lithography. The lateral dimensions are brought down to the 100 nm range by using silicon nitride (SiNx) spacers according to the basic process flow presented in Fig. 1.
Figure 1. (a) The SPE sequence. (b) Schematic cross section of the process flow.
Figure 2. (a) Controlled growth of SPE Si islands. In this case, a geometry has been chosen so that all the available α-Si is collected in the contact windows and practically no nucleation on the surrounding silicon dioxide is observed. The inset represents an high-resolution transmission electron microscopy (TEM) image of the growth interface. (b) Cross-sectional TEM image of SPE p+ Si island showing the Si crystal facets. The thicknesses of the Al transport layer and α-Si layer were 150 nm and 10 nm, respectively.
(CVD) SiNx spacers are formed in order to reduce the contact size down to the 100 nm range. The native silicon dioxide is removed from the Si surface by HF 0.55% just prior the physical-vapor deposition (PVD) of first Al and then α-Si thin films. The epitaxy is induced by a thermal anneal in an N2 gas flow and is fed from the top α-Si layer via a fast diffusion process in the Al transport layer [7]. From the HRTEM image shown in Fig. 2, it can be seen that the SPE-Si to Si-substrate interface is clean and atomically smooth, which substantiates that the crystal island growth is epitaxial.
SPE Si Doping
The SPE Si is highly p+-doped due to the incorporation of aluminum in substitutional lattice positions. For SPE processes, dopant incorporation is achieved during growth and higher doping than the solid-solubility reported in literature, which for Al in Si at 500 °C is about 1 – 3 × 1018 cm-3 [8], can be obtained. A quantitative analysis of the doping level in the SPE islands by secondary ions mass spectroscopy (SIMS) has not been possible due to the limited island size. However, high aluminum-doping levels were confirmed by the contact resistance measurements presented below as well as the SIMS analysis of a surface area of about 20 × 20 µm2 Si that contained a ~ 5 µm2 SPE island. This island was grown on an unpatterned <100> Si wafer and the Al/α-Si stack was also unpatterned, which renders a random distribution of SPE islands, like the one shown in the inset Fig. 3b. The overall coverage of the surface with SPE islands depends on the Al and α-Si thickness, which was, in this example, 150 nm and 10 nm, respectively, giving a coverage of about 4%. The abruptness of the doping transition has been verified by an in-house capacitance-voltage (C-V) doping profiling technique that uses an abrupt n+ buried layer to profile the tail of high-gradient B-doped layers at the wafer surface [9]. The basic test structure is shown in Fig. 3a. The measured profile of a large contact window with random SPE-Si island deposition is compared to that of a neighboring contact without deposition (i.e., a Schottky contact). The profiles are essentially identical confirming that, for a process temperature at 500 °C, the Al doping concentration is high to the interface and not further.
Electrical Characterization
The quality of the SPE-filled windows as a function of the growth temperature and the SPE-island physical dimensions (width and thickness) has been extensively investigated by fabricating and characterizing electrical devices: p+-n diodes, p+ contacts, and p+-emitters for p-n-p BJTs.
PN Junctions
The p+-n diodes are formed on n-Si by SPE of islands such as the one shown in Fig. 4a. The I-V diode characteristics are near-ideal with ideality factors of about 1.03, even when the junction area is shrunk down to 200 × 200 nm2.
Figure 4. (a) SEM micrograph of the contact window after silicon SPE (and Al removal). The inset shows the original contact window (dark center region). The scale bar is 200 nm. (b) Current-voltage characteristics of a 200 × 200 nm2 junction fabricated on an n-type substrate by SPE at 400 °C. The inset presents a schematic cross-section of the measured devices: when SPE is performed, a p+n diode characteristic is measured. Without SPE, Al/Si(1%) metallization to n-doped silicon gives a Schottky diode characteristic.
The very low leakage current of the SPE p+-n junctions clearly demonstrates a very low density of defects and associated generation/recombination centers in the depletion region. This confirms that the epitaxial process is practically defect-free since the metallurgic junction lies at the point where the deposition starts, i.e. the substrate to island interface.
Contact Resistance
p+ SPE Si was found to be at most 10-7 Ωcm2, and it increases when the deposition temperature is decreased as seen in Fig. 5a. This is presumably due to a decrease of dopant incorporation during epitaxy at lower temperatures.
The influence of the Al/α-Si etch-definition, as defined in Fig. 1a, on the contact resistance measurements has also been studied. The results, presented in Fig. 5b, show that the contact resistance decreases when the Al/α-Si etch-definition increases. This is due to the fact that the overgrowth on the SiO2 increases when the Al/α-Si etch-definition increases, i.e., when the amount of Si available for the growth increases. In that case, the SPE-island contact area to metallization increases, and thus the resistance of the contact as a whole decreases.
Figure 5. Contact resistance of SPE p+ filled contacts measured on special Kelvin test structures as a function of (a) SPE growth temperature and (b) etch-definition for 2 different SPE temperatures. The island thickness is 200 nm.
Laterally-contacted SPE-Si resistors, about 500 to 1000 nm long, were also fabricated and electrically characterized. The resistor size is difficult to determine precisely and the carrier mobility in Al-doped silicon is not well-known but the measured values lie in the range that would be expected of a doping level around 1 − 3 × 1018 cm-3.
Emitter for Bipolar Junction Transistors
surrounding silicon dioxide, as well as a slower diffusion of α-Si through the metal transport layer.
Figure 6. (a) SEM micrograph of an SPE 1.2 × 1.2 µm2
p+ emitter on which lateral overgrowth on the silicon dioxide is visible. (b) Base currents of devices with different emitter areas. The thickness of the emitters, obtained by SPE at 500 °C, was 100 nm.
Figure 7. Measured forward Gummel plots of p+-n-p devices with an area of 0.7 × 0.7 µm2, (a) for two different thicknesses of the p+ emitter and (b) for a 200-nm-thick SPE emitter grown at two different temperatures. In all cases, the collector-base voltage VBC = 0 V and the base doping is 2 ×1017 cm-3.
Conclusion
contact window sizes. An optimization towards nanoscale contact window sizes is therefore necessary to preserve a high diode quality under these more extreme conditions. However, in view of the properties achieved for a processing temperature of only 400 °C, this technique is a versatile CMOS compatible module for location- and dimension-controllable selective p+-Si growth for both front- and back-end processes.
Acknowledgments
The authors would like to thank P. Hadley for fruitful discussions and the staff of the DIMES-ICP cleanrooms, in particular E. J. G. Goudena for general support, C. R. de Boer for his contribution to the processing, as well as P. J. F. Swart for his assistance with the electrical measurements. This research is supported by the Dutch Foundation for Fundamental Research on Matter (FOM).
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