Description
The CXD8302Q has the functions needs to configure a PLL circuit with a timing generator and external sync signals for a CCD of 480K pixels (EIA, effective pixels) and 570K pixels (CCIR, effective pixels).
Features
• EIA and CCIR compatible
• Compatible with component digital and composite digital recording format
• Both SYNC and VD/HD signals can be used for external sync signals
Absolute Maximum Ratings
• Supply voltage VDD VSS– 0.3 to +7 V
• Input voltage VI VSS– 0.3 to VDD+ 0.3 V
• Storage temperature Tstg –40 to +125 °C Recommended Operating Conditions
• Supply voltage VDD 4.5 to 5.5 V
• Operating temperature Topr 0 to 70 °C Block Diagram
Applications CCD cameras Structure
Silicon gate CMOS IC
PLL for CCD Cameras
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
44 pin QFP (Plastic)
2fH
V reset
8
fH
fV
Separation of fH and fV
Frequency Division EIA : 1/525 CCIR: 1/625
Latch
65 Clocks Delay
INTfH
HD VD SYNC BLK EXTSYNC
EXTHD
MODE1
EIA/CCIR
CLKI CLKO
EXTfH
EXTVD
INTfH phase setting V latch
MODE2
H timing
V timing
Frequency Division EIA : 1/572 (1/568)
CCIR: 1/576 (1/567) 15
14 13
26
31
32
38
2 3 4 7 8 9 10 11
37 44 43 42 41 20 19
Pulse Generation Circuit
Vss TEST7 NC CLKO
HD
BLK CLKI VDD
Vss
VD SYNC
Vss DLY0 DLY1 DLY2 VDD Vss DLY3 DLY4 DLY5 DLY6 DLY7
Vss EXTVD EXTHD EXTSYNC Vss VDD
TEST1 EXTfH INTfH TEST2 TEST3
NC EIA/CCIR MODE2 TEST6 VDD Vss TEST5 MODE1 TEST4 NC Vss
2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22 24 23
25 26 27 28 29 30
40 39 38 37 36 35 34
32 31 33
41 42 43 44
1
Pin Configuration
Pin Description
Pin No. Symbol I/O Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
VSS
DLY0 DLY1 DLY2 VDD
VSS
DLY3 DLY4 DLY5 DLY6 DLY7 VSS
EXTVD EXTHD EXTSYNC VSS
VDD
TEST1 EXTfH
INTfH
TEST2 TEST3 VSS
NC TEST4 MODE TEST5 VSS
VDD
TEST6 MODE2 EIA/CCIR NC VSS
TEST7 NC CLKO
— I I I
—
— I I I I I
— I I I
—
— O O O O O
—
— I I I
—
— I I I
—
— O
— O
Pin 20 (INTfH) phase setting. (With pull-up resistor) Pin 20 (INTfH) phase setting. (With pull-up resistor) Pin 20 (INTfH) phase setting. (With pull-up resistor)
Pin 20 (INTfH) phase setting. (With pull-up resistor) Pin 20 (INTfH) phase setting. (With pull-up resistor) Pin 20 (INTfH) phase setting. (With pull-up resistor) Pin 20 (INTfH) phase setting. (With pull-up resistor) Pin 20 (INTfH) phase setting (MSB). (With pull-up resistor)
External VD input. (With pull-up resistor)
External HD input. (With pull-up resistor)
External SYNC input. (With pull-up resistor)
Test output (normally OPEN).
External fHoutput.
Internal fHoutput.
Test output (normally OPEN).
Test output (normally OPEN).
Test input (normally High). (With pull-up resistor) High: SYNC sync mode, Low: VD/HD sync mode. (With pull-up resistor) Test input (normally Low). (With pull-down resistor)
Test input (normally High). (With pull-up resistor) High: Component digital mode, Low: Composite digital mode.
(With pull-up resistor) High: EIA mode, Low: CCIR mode. (With pull-up resistor)
Test output (normally OPEN).
Inversed output of CLKI.
Pin No. Symbol I/O Description 38
39 40 41 42 43 44
CLKI VDD
VSS
HD VD SYNC BLK
I
—
— O O O O
Clock input (from timing generator).
Horizontal sync signal output.
Vertical sync signal output.
Sync signal output.
Blanking pulse output.
Electrical Characteristics
1) DC characteristics (VDD= 5V ± 0.25V, Topr = 0 to 70°C, VSS= 0V)
Item Symbol
VIH
VIL
IIN1
IIN2
IIN3 VOH
VOL
Conditions
VI= VDD
VI= VSS
IOH= –2mA IOL= 4mA
Min.
0.7VDD
–10
10
–8 2.4
Typ. Max.
0.3VDD
Unit V V µA
µA
µA V V
±1
35
–30 4.5 0.2
10
120
–100
0.4 High
Low
High Low Input voltage
Input current 1
(Input pins other than those below) Input current 2
(Input pins with pull-up resistor) Input current 3
(Input pins with pull-down resistor) Output voltage
2) AC characteristics
Vertical reset in VD/HD sync mode
The phase of EXTVD should be input as shown in the diagram below against the first equivalent pulse during vertical blanking period.
(Take care as the following conditions might not be satisfied depending on the phase setting of INTfHif the phases are locked when the falling phase shifts a lot between EXTfHand INTfH.)
81 clocks 81 clocks
SYNC
EXTVD
The EXTVD should fall at the timing shown with the slashes.
Description of Operation 1) Operation overview
• Functions as sync signal generator
Each of fH(INTfH), VD, HD, SYNC, and BLK pulses is generated from clocks input by the timing generator.
These pulses are generated by free running if external sync signals are not input.
• External synchronization function (PLL)
When the SYNC (EXTSYNC) or VD/HD (EXTVD/EXTHD) external sync signal is input, the vertical reset is compulsorily triggered on each of the fH (INTfH), VD, HD, SYNC, and BLK pulses, and fH (EXTfH) is simultaneously generated according to the external sync signal. Phase comparison is done externally between INTfHand EXTfHand a PLL circuit is configured, then the timing generator is synchronized with an external sync signal.
EIA/CCIR 32 CCIR EIA
Symbol Pin No. L H
MODE1 26
MODE2 31
VD/HD sync mode:
EXTVD/EXTHD is used as the external sync signal, and the EXTHD signal becomes EXTfH.
Composite digital mode;
Clock frequency input by timing generator EIA 17.897725MHz (1137.5fH= 5fsc) CCIR 17.734475MHz
(1135 + 4/625fH= 4fsc)
SYNC sync mode:
EXTSYNC is used as the external sync signal, and the EXTfHis obtained by separating it from EXTSYNC
Component digital mode:
Clock frequency input by timing generator EIA 18MHz (1144fH)
CCIR 18MHz (1152fH) 2) Mode setting
The phase relationship between external sync and EXTfHin each sync mode is shown below.
• VD/HD sync mode
The rise and fall timings of EXTHD signal are directly reflected on EXTfH.
• SYNC synchronous mode
The fall timing of EXTSYNC is the fall timing EXTfH, but the rise timing of EXTfHis generated by counting the number of clocks input by the timing generator. Therefore, make sure to compare phases of fall timing of between EXTfHand INTfHfor PLL configuration in the SYNC synchronous mode.
EXTHD
EXTfH
EXTSYNC (HSYNC)
EXTfH
42 clocks 42 clocks
3) I/O pin capacitance (VDD= 5V ± 0.25V, Topr = 0 to 70°C, VSS= 0V)
Item Symbol
CIN
Min.
2.0 4.0
Typ. Max. Unit
pF pF Input pin capacitance
COUT
Output pin capacitance
Example of System Configuration
13 14 15
26
19 20 33
38 41 42
7 6 5 Separation
of fH and fv
Phase
Comparator LPF VCO
Frequency Division/
Pulse Generation Circuit
1/2 Frequency Division
Pulse Generation Circuit CLK
HD VD
CXD8302Q CXD2422R (TG)
INTfH
EXTfH
fH
fV
SYNC
HD VD MODE1 External sync signal
Electronic shutter serial data
XH1, 2 XRG XSUB XV1 to 4 XSG1, 2 SHP, SHD HCLP1, 2 VCLP PBLK
To each driver
To signal processing circuit 36MHz (Component digital)
35.79545MHz (Composite digital, EIA) 35.56895MHz (Composite digital, CCIR)
Note) 1. Either SYNC or VD/HD is used as the external sync signal. When SYNC is used (SYNC synchronous mode), fix MODE1 to High; when VD/HD is used (VD/HD synchronous mode), fix MODE1 to Low.
2. Be sure to do phase comparison of the falling edge of EXTfH and INTfH for SYNC synchronous mode.
3) INTfHphase setting
In either VD/HD or SYNC sync mode, the INTfHphase should be adjusted in line with the phase variance of EXTfH, which forms the reference for phase comparison. The INTfHphase may be adjusted against VD, HD, SYNC and BLK pulses using DLY0 to DLY7, respectively. (The state of INTfHand EXTfHphases fixed by PLL leads to phase adjustment of VD, HD, SYNC, and BLK pulse against the external sync signal.)
The INTfHis set to the phase being delayed (DELAY-64) clocks from that of HD.
DELAY = 0 to 255: to be set in 8-bit binary with DLY7 as MSB. High: 1, low: 0.
INTfH
HD
128 clocks
128 clocks (DELAY – 64) clocks
Timing Chart (1) EIA vertical direction HD VD SYNC BLK
Odd Field 9H 20H HD VD SYNC BLK
Even Field 9H 20H
Timing Chart (1) EIA vertical direction HD VD SYNC BLK
Odd Field 9H 20H HD VD SYNC BLK
Even Field 9H 20H
Number of clocks HD HSYNC EQ VSYNC H BLK
EIA 128 11127 27 27
69 –57 0
196 (Component digital mode) 195 (Composite digital mode)
050100150200–50 0 Number of clocks HD HSYNC EQ VSYNC H BLK
CCIR 128 11329 29 29
71 –55 0
217 (Component digital mode) 214 (Composite digital mode)
050100150200–50 0
Clock frequency 18MHz (Component digital mode) 17.897725MHz (Composite digital mode, EIA) 17.734475MHz (Composite digital mode, CCIR)
Timing Chart (2) CCIR vertical direction
Package Outline Unit: mm
SONY CODE EIAJ CODE JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
EPOXY RESIN SOLDER PLATING 42 ALLOY 12.4 ± 0.4
10.0 ± 0.1
33 23
22
12
11 1
34
44
0.8 ± 0.15 0.3 ± 0.1
C0.6
1.75
0.8 ± 0.05 0.8 ± 0.05
0.15 ± 0.05
10.76
A 11.24 ± 0.20.58 ± 0.2
5°
13°
0.53
0.15– 0.15 MAXMAXMIN
0.35 ± 0.15
5°+ 2°
– 5°
DETAIL A
44PIN QFP (PLASTIC)
QFP-44P-L221
∗QFP044-P-1010-B
0.4g
