HV209

General Description

The Supertex HV209 is a 200V low charge injection 12- channel high voltage analog switch configured as 6 SPDT analog switch intended for medical ultrasound applications.

Bleed resistors are integrated on the output switches to eliminate charge built up on the piezo electric transducers.

The bleed resistors are at a nominal value of 35KΩ. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to pro- vide efficient control of high voltage analog signals. The outputs are configured as single pole double throw analog switches. Data is shifted into a 6-bit shift register using an external clock. The LE latches the shift register data into the individual switch latches. A logic high connects a switch common Y_X to SW_X. A logic low connects Y_X to SW_X. A logic hi in CL resets all switches to SW_X simultaneously.

V_PP – V_NN

200V HV209FG HV209X

HV209

12-Channel High Voltage Analog Switch

Features

❏ HVCMOS technology for high performance

❏ Operating voltage of up to 200V

❏ Output On-resistance typically 22Ω

❏ Integrated bleed resistors on the outputs

❏ Very low quiescent power dissipation -10µA

❏ Low parasitic capacitances

❏ -58dB typical output off isolation at 5MHz

❏ 5.0V to 12V CMOS logic circuitry

❏ Excellent noise immunity

❏ Flexible high voltage supplies

Absolute Maximum Ratings*

V_DD Logic power supply voltage -0.5V to +15V V_PP - V_NN Supply voltage +220V V_PP Positive high voltage supply -0.5V to +200V V_NN Negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to V_DD +0.3V V_SIG Analog Signal Range V_NN to V_PP Peak analog signal current/channel 3.0A Storage temperature -65°C to +150°C

Power dissipation 1.0W

* All voltages are referenced to ground. Absolute maximum ratings are those values which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the

Ordering Information

Package Options

48-pin TQFP Die

2

Electrical Characteristics

DC Characteristics (over recommended operating conditions unless otherwise noted)

30 26 38 48 I_SIG = 5mA V_PP = 40V,

25 22 27 32 I_SIG = 200mA V_NN = -160V

Small Signal Switch (ON) R_ONS 25 22 27 30 ohms I_SIG = 5mA V_PP = 100V,

Resistance

18 18 24 27 I_SIG = 200mA V_NN = -100V

23 20 25 30 I_SIG = 5mA V_PP = 190V,

22 16 25 27 I_SIG = 200mA V_NN = -10V

Small Signal Switch (ON) ∆R_ONS 20 5.0 20 20 % I_SW = 5mA, V_PP = 100V,

Resistance Matching V_NN = -100V

Large Signal Switch (ON) R_ONL 15 ohms V_SIG = V_PP - 10V, I_SIG = 1A

Resistance

Output Switch Shunt R_INT 20 35 50 Kohms Output switch to R_GND

Resistance

DC Offset Switch Off 50 50 50 mV No Load, R_GND = 0V

DC Offset Switch On 50 50 50 mV No Load, R_GND = 0V

Pos. HV Supply Current I_PPQ 10 50 µA ALL SWs OFF

Neg. HV Supply Current I_NNQ -10 -50 µA ALL SWs OFF

Pos. HV Supply Current I_PPQ 10 50 µA ALL SWs ON I_SW = 5mA

Neg. HV Supply Current I_NNQ -10 -50 µA ALL SWs ON I_SW = 5mA

Switch Output 3.0 3.0 2.0 2.0 A V_SIG duty cycle ≤ 0.1%

Peak Current

Output Switch Frequency f_SW 50 KHz Duty Cycle = 50%

6.5 7.0 8.0 V_PP = 40V,

V_NN = -160V

I_PP Supply Current I_PP 4.0 5.0 5.5 mA V_PP = 100V,

V_NN = -100V

4.0 5.0 5.5 V_PP = 190V,

V_NN = -10V

6.5 7.0 8.0 V_PP = 40V,

V_NN = -160V

I_NN Supply Current I_NN 4.0 5.0 5.5 mA V_PP = 100V,

V_NN = -100V

4.0 5.0 5.5 V_PP = 190V,

V_NN = -10V

Logic Supply I_DD 4.0 4.0 4.0 mA f_CLK = 5MHz, V_DD = 5.0V

Average Current

Logic Supply I_DDQ 10 10 10 µA

Quiescent Current

Data Out Source Current I_SOR 0.45 0.45 0.70 0.40 mA V_OUT = V_DD - 0.7V

Data Out Sink Current I_SINK 0.45 0.45 0.70 0.40 mA V_OUT = 0.7V

Logic Input Capacitance C_IN 10 10 10 pF

0°^{C +25}°^{C +70}°^C

Characteristics Sym Units Test Conditions

min max min typ max min max

50KHz Output Switching Frequency

with no load

Electrical Characteristics

AC Characteristics (over operating conditions V

= 5V, unless otherwise noted)

0°^{C +25}°^{C +70}°^C

Characteristics Sym

min max min typ max min max Units Test Conditions

Set Up Time Before LE Rises t_SD 150 150 150 ns

Time Width of LE t_WLE 150 150 150 ns

Clock Delay Time to Data Out t_DO 150 150 150 ns

Time Width of CL t_WCL 150 150 150 ns

Set Up Time Data to Clock t_SU 15 15 8.0 20 ns

Hold Time Data from Clock t_h 35 35 35 ns

Clock Freq f_CLK 5.0 5.0 5.0 MHz 50% duty cycle

f_DATA = f_CLK/2

Turn On Time t_ON 5.0 5.0 5.0 µs V_SIG = V_PP -10V,

R_L = 10KΩ

Turn Off Time t_OFF 5.0 5.0 5.0 µs V_SIG = V_PP -10V,

R_L = 10KΩ

20 20 20 V_PP = 40V,

V_NN = -160V

Maximum V_SIG Slew Rate dv/dt 20 20 20 V/ns V_PP = 100V,

V_NN = -100V

20 20 20 V_PP = 190V,

V_NN = -10V

Off Isolation KO -30 -30 -33 -30 dB f = 5MHz,

1KΩ//15pF load

-58 -58 -58 dB f = 5MHz,

50Ω load

Switch Crosstalk K_CR -60 -60 -70 -60 dB f = 5MHz,

50Ω load

Output Switch Isolation I_ID 300 300 300 mA 300ns pulse width,

Diode Current 2.0% duty cycle

Off Capacitance SW to GND C_SG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, 1MHz

On Capacitance SW to GND C_SG(ON) 25 50 25 38 50 25 50 pF 0V, 1MHz

Positive Output Voltage Spike +V_SPK 150 150 150 mV R_LOAD = 50Ω

Negative Output Voltage Spike -V_SPK 150 150 150 mV R_LOAD = 50Ω

4

Data Inputs Switch States

DO D1 D2 D3 D4 D5 LE CL

Y0 Y1 Y2 Y3 Y4 Y5

L L L SW0

H L L SW0

L L L SW1

H L L SW1

L L L SW2

H L L SW2

L L L SW3

H L L SW3

L L L SW4

H L L SW4

L L L SW5

H L L SW5

X X X X X X H L

X X X X X X X H SW0 SW1 SW2 SW3 SW4 SW5

Symbol Parameter Value

V_PP Positive high voltage supply¹ +40V to V_NN+ 200V

V_NN Negative high voltage supply¹ -10V to -160V

V_DD Logic power supply voltage¹ +4.5V to +13.2V

V_IH High-level input voltage 0.8 V_DD to V_DD

V_IL Low-level input voltage 0V to 0.2V_DD

V_SIG Analog signal voltage peak-to-peak² V_NN +10V to V_PP -10V

T_A Operating free air-temperature 0°C to 70°C

Notes:

1 Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.

2 V_SIG must be within V_PP and V_NN voltage range or floating during power up/down transition.

Operating Conditions

Truth Table

HOLDS PREVIOUS STATE

DC Offset ON/OFF

VPP 5V

V_NN

VPP

V_NN

VDD

GND V_OUT

T_ON/T_OFF Test Circuit

VPP 5V

VNN

VPP

VNN

VDD

GND VPP –10V

R_L 10KΩ

VOUT

Isolation Diode Current

IID

VPP 5V

VNN

VPP

VNN

VDD

GND V_NN

V_SIG

Crosstalk

KCR = 20LogV_OUT VIN

V_IN = 10 V_P–P

@5MHz

NC 50Ω

VPP 5V

VNN

VPP

VNN

VDD

GND 50Ω

Charge Injection

VPP 5V

VNN

VPP

VNN

VDD

GND V_SIG

V_OUT 1000pF

Q = 1000pF x ∆VOUT

∆VOUT

Output Voltage Spike

V_PP 5V

V_NN

V_PP

V_NN

V_DD

GND V_OUT

1KΩ R_L 50Ω +VSPK

–V_SPK

OFF Isolation

KO = 20Log V_OUT V_IN VIN = 10 VP–P

@5MHz

V_PP 5V

VNN

V_PP

VNN

V_DD

GND RL

V_OUT

Test Circuits

6

DATA IN

LE

CLOCK

DATA OUT

OFF

ON OUT (TYP) V

50% 50%

50%

50%

t_WLE

t_SD

t_SU t_h

50%

50%

t_OFF 50%

t_DO

t_ON

t_WCL CLR

D_{N – 1} D_N D_{N + 1}

50%

50%

90%

10%

Logic Timing Waveforms

Block Diagram

SW2

SW3

SW4

SW5 SW0

Y0

SW0

Y1

SW1

CL CLK

V_DD

D_OUT D_IN

GND

6 BIT SHIFT REGISTER

V_PP V_NN

High Voltage Level Translator

High Voltage Level Translator

High Voltage Level Translator

High Voltage Level Translator

High Voltage Level Translator

High Voltage Level Translator

LE D LE CL

D LE CL

D LE CL

D LE CL

D LE CL

D LE CL

SW1

Y2

SW2

Y3

SW3

Y4

SW4

Y5

SW5

R_GND1 / R_GND2

8

Pin Configuration

HV209 48-Pin TQFP Pin Function

1 N/C

2 SW0

3 Y0

4 SW0

5 N/C

6 SW2

7 Y2

8 SW2

9 N/C

10 SW4 11 Y4 12 SW4 13 N/C 14 N/C 15 N/C 16 V_NN 17 N/C 18 N/C 19 N/C 20 N/C 21 V_PP 22 N/C 23 N/C 24 N/C

Pin #1

Pin 1

top view 48-pin TQFP

Pin 12

Pin Function 25 SW5 26 Y5 27 SW5 28 N/C 29 SW3 30 Y3 31 SW3 32 N/C 33 SW1 34 Y1 35 SW1 36 N/C 37 R_GND1 38 N/C 39 D_OUT 40 V_DD 41 D_IN 42 CLR 43 LE 44 CLK 45 GND 46 N/C 47 N/C 48 R_GND2

Package Outline

HV209

1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com

09/30/02

©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.