Design of RF Oscillators for Wireless Digital Transmitters

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Design of RF Oscillators for Wireless

Digital Transmitters

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Design of RF Oscillators for Wireless

Digital Transmitters

Proefschrift

ter verkrijging van de graad van doctor aan de Technische Universiteit Delft,

op gezag van de Rector Magnificus prof. ir. K.C.A.M. Luyben, voorzitter van het College voor Promoties,

in het openbaar te verdedigen

op maandag 28 september 2015 om 12:30 uur

door

Seyed Amir Reza AHMADI MEHR

Master of Science in Electrical Engineering, University of Tehran, Iran geboren te Isfahan, Iran.

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Dit proefschrift is goedgekeurd door de promotor: Prof. dr. R. B. Staszewski Samenstelling promotiecommissie:

Rector Magnificus, voorzitter

Prof. dr. R. B. Staszewski, Technische Universiteit Delft Independent members:

Prof. dr. ing. L. C. N. de Vreede, Technische Universiteit Delft Prof. dr. J. R. Long, Technische Universiteit Delft Prof. dr. K. A. A. Makinwa, Technische Universiteit Delft Prof. dr. ir. F. E. van Vliet Universiteit Twente,

Prof. dr. ing. S. Heinen, RWTH Aachen University, Duitsland

Dr. M. Acar, NXP semiconductor

Seyed Amir Reza Ahmadi Mehr,

Design of RF Oscillators for Wireless Digital Transmitters, Ph.D. Thesis Delft University of Technology,

with summary in Dutch.

Keywords: all-digital phase-locked loop (ADPLL), basestation, class-C, class-D, digitally controlled oscillator, frequency pulling, frequency resolution, injection locking, phase noise, quadrature signal, RF, series LC-tank, transmitter.

ISBN 978-94-6259-849-2

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the prior written permission of the copyright owner.

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To my beloved parents, Hossein and Nahid To my beloved sisters, Marjan and Leila To my beloved brother, Ehsan And last, but not least, to my lovely wife Maede and her respected family

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“Genius is one percent inspiration and ninety-nine percent perspiration.”

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C h a p t e r

1

Introduction

There is an abundance of growth in cellular and wireless communications, which stimulates industrial researchers and academia to initiate further studies that focus on evaluating the performance of wireless systems and developing new architectures and technologies to overcome limitations. These limitations include meeting the growing demands for higher data rates while maintaining mobility. The standards in consideration include LTE for cellular applications, which can achieve up to 300 Mbps data rate for the downlink [1]. As an example, the cellular handset market was expected to ship a total volume in excess of 1.9 billion mobile phones worldwide in 2014, which is expected to increase by several percent in 2015 [2]. Furthermore, the next booming technology, expected to fully emerge in less than a decade, is Internet-of-Things (IoT). The microelectronic integrated circuits chip, as always, plays a critical role in this technology, of which tens of billions will be required in half a decade1. Consequently, this prompts researchers to explore a new realm of radio frequency integrated designs, systems and design approaches to satisfy the future needs. The following information, briefly elaborates on the differences between analog and digital approaches during recent years, their advantages and trade-offs.

1.1 Is Analog/RF Doomed to Digitization?

Over the past recent years, radio frequency (RF) CMOS integrated circuits have progressively evolved primarily due to the rapid improvement of CMOS technology, which afforded the ability to

1_{http://www.freescale.com/}

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2 Introduction Digital Capability Raw analog performance Combined

CMOS node

Per

fr

o

ma

n

ce

/Ca

p

a

b

ili

ty

Figure 1.1: Effect of CMOS process advancement on digital and, ultimately, RF performance [3]. realize various new architecture. The use of advanced CMOS processes allows for a great degree of scaling and integration in digital circuitry but complicates the implementation of traditional RF and analog circuits. On the other hand, in order to support the increasing levels of system-on-chip (SoC) integration required by consumers and the explosive growth of wireless communications, the RF circuit should progress towards the finer CMOS process technology where the enormous potential of cheap digital logic and memory can be exploited. Unfortunately, the benefits of digital scaling are not shared by traditional RF circuits. The continuous scaling of the CMOS technology has had negative effect on the linear capabilities of analog transistors. To maintain the reliability of scaled-down MOS devices, the supply voltage must be reduced, while the threshold voltage is kept relatively constant. This has an adverse effect on available voltage margin when the transistors are intended to operate as current sources [3]. In scaled CMOS, channel resistance rds degraded,

severely reducing the quality of MOS current sources and the intrinsic voltage gain g_m× r_ds. In addition, due to the thin gate dielectric becoming ever thinner, large high-density capacitors realized as MOS switches are becoming leaky, which subsequently prevents an efficient implementation of low-frequency baseband filters and charge-pump PLL loop filters [3]. Entering the digitally assisted approaches provides analog/RF circuitry with calibration, compensation, linearization, and pre-distortion which can better improve the system performance to the point and is more reliable than the conventional. Furthermore, digital circuits are more repeatable, predictable, and testable.

The above observation is graphically depicted in Fig. 1.1. The raw analog performance based on the traditional linear transistor operation worsen with each process node. On the other hand, the raw digital capability, in terms of processing and speed, is improving. This demonstrates that the new, powerful, inexpensive, digital logic and memory cannot compensate for the impairment of analog performance. The primary reason is the complexity of the transceiver component interaction which possibly to calibrate or compensate for single parameter degradation. A degraded component typically affects multiple of parameters, which are very difficult, or even impossible, to simultaneously

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1.2 Aim and Scope 3

Figure 1.2: Qualcomm RTR8600 multi-band/mode RF transceiver in the Apple iPhone 51. calibrate [3]. However, there is a relentless push towards system-level integration and, recently, multi-core radio integration facilities manufacturing less bulky equipment that is much less expensive and consumes less power, while, at the same time, allowing multiple radios to simultaneously coexist within a single silicon die. Normally, the majority of the area of commercial RF-SoC’s is occupied by digital logic and memory in order to implement the digital baseband together with various controller and application processor functionalities. For this reason, logic and memory determine the technology choice which is not favorable to the linear RF operation.

These ever-increasing levels of system-on-chip (SoC) integration create new challenges for designers in several aspects. Fig. 1.2 illustrates the Qualcomm RTR8600 multi-band/mode RF transceiver in the Apple iPhone 5. The RTR8600 is paired alongside the MDM9615 to support various bands including five UMTS bands and over five LTE and four EDGE bands which fully show multi-band radio integration. It is evident that many on chip transformers and inductors were used, which complicates the SoC designs. These challenges that are associated with integration must be handled by new techniques which will be the focus here in this dissertation.

1.2 Aim and Scope

The overall aim of this dissertation is to explore modern digital transmitters with a focus on the most challenging and important circuitry, which is a digitally controlled oscillator (DCO). A DCO has several important specifications that are required by the targeted wireless communication standards. The first subgoal is to analyze the limitations and strong points of the digital transmitter and then

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4 Introduction

elaborate on the specification of each block in the transmitter path. Secondly, we will substantiate that new emerging standards and architectures impose harsh constraints on the oscillator design. A DCO has various design parameters, such as phase noise, power consumption, frequency resolution, pulling immunity, and quadrature signal generation and its accuracy. Several commonly used architectures will be reviewed to fulfill the required specifications.

1.3 Original Contributions

The original contributions of this work are:

• system level discussions and considerations on building a modern digital transmitter based on an all-digital PLL (Chapter 2);

• proposing an efficient low-power system-level solution for virtually pulling-free operation of a two-channel system including a prospect for multi-radio SoC designs (Chapter 3);

• an analysis and design of a dual-core oscillator to achieve very low phase noise with an insight into multi-core oscillator designs (Chapter 4);

• an analysis and design of a quadrature series-LC-tank ring oscillator with a very fine frequency resolution and good quadrature accuracy (Chapter 5);

• a design of a very small series LC-tank ring oscillator with the best FoM and almost an octave tuning range (Chapter 5).

1.4 Thesis Organization

This thesis is organized as follows. A common background for the research is described in Chapter 2. It contains a discussion about an efficient method of implementing a phase modulator which would be suitable for a high efficiency polar or outphasing transmitter. Furthermore, an all-digital PLL (ADPLL) based transmitter is discussed as a potential solution. The main building blocks of the transmitter are discussed, and it will become obvious that the DCO is the most critical circuitry which limits the spectral purity.

As integration is the main driving force for cost reduction, however this imposes many coupling issues for different parts of the transceiver such as the local oscillator. This problem is known as pulling, which will likely be the primary cause of the degrading spectral purity of the TX output in multi radio SoCs. This issue is addressed in Chapter 3. A low power digital fractional divider proposed and mismatch analysis was done to incorporate the nonideality of these phase switched dividers.

Another issue arises with the phase noise of the DCO, especially for the basestation applications, which normally use several expensive external components to meet the stringent specifications. In Chapter 4, the first CMOS oscillator which is able to meet the most strict specification of basestation

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1.4 Thesis Organization 5

is introduced. Using a parallelism approach provides an opportunity to further reduce the phase noise which eliminates the limitation for single core oscillators.

Chapter 5 addresses the need for a high purity DCO with a high accuracy quadrature signal and also a very fine frequency resolution without any extra effort. These are required in designing a high efficiency transmitter. This chapter also introduces a new topology for an oscillator that is based on the series LC-tank. Thanks to the single ended implementation, it enjoys better quadrature accuracy. Furthermore, this topology is used with a low inductor quality factor and has achieved the best noise performance among the other conventional ring oscillators with almost the same size and tuning range.

Finally, a summary of the main contributions of this work, together with sensible suggestions for future developments, are provided in Chapter 6.

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C h a p t e r

2

Transmitter Architecture Considerations

The technical background relevant to this work is described in this chapter. Additionally, it contains the number of different sets of simulations to provide more insight into the system level specifications. Section 2.1 briefly describes different transmitter architecture. Section 2.2 continues with the various kinds of phase modulator, which is the main building block of the high efficiency transmitter. Section 2.3 and 2.4 elaborate on different building blocks and their imperfections in digitally assisted transmitters which affect the RF performance.

2.1 Digital Transmitter Architectures

2.1.1 Design Criteria for a Transmitter

A radio transmitter design must meet certain requirements. These include the frequency of operation, modulation scheme, and purity of the transmitted signal, power efficiency, and output power level. The primary design criteria for a transmitter can be categorized as according to the following information.

2.1.1.1 Out-of-band Emission

In a transmitter, the operation band of the transmitter is very wide since several standards at various bands must be covered. Hence, using rejection filters at the output of the transmitter are not practical. As a result, each design must be made based on the essential requirement of low

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8 Transmitter Architecture Considerations

out-of-band emissions to avoid using any extra external filtering components.

2.1.1.2 Cost of the Circuit

Regardless of the standard for which the transmitter is used, minimizing the cost has always been one of the highest priorities. To reduce the cost, the entire analog and digital baseband and radio frequency (RF) circuits must be integrated onto a single chip with a minimum number of external components. The next step for cost efficiency is to design a big portion of the system in the digital domain. Moreover, an all-digital solution can benefit from the technology scaling. It also enjoys a high reconfigurability, which facilitates using the same hardware for various standards.

2.1.1.3 Power Efficiency

The most power hungry component of a transmitter, the power amplifier (PA), provides a high power RF signal to the antenna. Reducing the power consumption of a transmitter is highly dependent on the power efficiency of the amplifier. Unfortunately, amplifiers suffer from a stringent trade-off between linearity and power efficiency. Many of the modulation schemes are being used, not because they effectively use the bandwidth, but to be compatible with nonlinear amplification to achieve higher power efficiency. However the growing needs for wider bandwidth lead to more efficient modulation schemes, however, linear amplifiers are required. For example, a power amplifier with 40% efficiency with an output power of 26 dBm (400 mW) will dissipate almost 1 W, which demonstrates the importance of the power efficiency.

2.1.2 Brief Overview of Modern Digital Transmitters

The principal challenge in transmitter design continues to lie in efficient, linear power amplifica-tion. Higher data rates demand more complex modulation schemes and hence greater linearities. In order to resolve the efficiency degradation problems in linear PAs, various efficient system level architectural enhancements have been proposed to linearize the transmitter. Fig. 2.1 compares three major linear amplification techniques. A polar transmitter is one of the most promising architectures for improving efficiency. Polar transmitter demonstrates a much higher power efficiency by basically operating by converting complex I/Q symbols into envelope and constant-envelope phase signals. The constant-envelope signal is amplified through a highly efficient nonlinear PA with a separate envelope control path. However, despite the efficiency improvement, the separate amplitude modulation through a low-dropout (LDO) regulator, DC/DC converter, or pulse width modulation (PWM) has significant bandwidth limitation and efficiency degradation problems in commercial wideband systems [4,5].

The outphasing power amplification, also referred to as linear amplification using nonlinear components (LINC), was proposed as another solution that may afford high efficiency with good linearity [6,7]. LINC eliminates the high linearity demands on a single PA by summing the outputs of two nonlinear PAs via a power combiner to amplify non-constant envelope signals. Also, the

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2.2 Phase Modulator 9 RFC Input RF Linear PA Transmitter Polar Envelop Modulator PA Input RF Polar Transmitter SCS Input RF PA1 PA2 Outphasing Transmitter

C

o

m

p

le

xi

ty

Efficiency

Figure 2.1: Comparison of linear amplification techniques.

outphasing transmitter, which uses two simple wideband switching PAs, can be a good solution for highly power efficient and wideband operation. However, power combining is still a challenge.

Power consumption (or power efficiency) of a power amplifier is the key contributor to the total power consumption of a transmitter which is highly dependent on the modulation scheme. New communication standards, such as LTE, have wide signal bandwidth and high peak-to-average-power ratio which demand high efficiency power amplifier. Therefore, high-efficiency architectures, such as polar [4,5] and outphasing [6,7], are preferred. One of the key components in these architectures is phase modulator. In the next section, we elaborate on different phase modulators.

2.2 Phase Modulator

The least complicated implementations of phase modulation is applying the modulation data to the control voltage of a voltage-controlled oscillator (VCO). This is an open-loop technique and inherently wideband. However, it inadvertently experiences frequency drift and VCO nonlinearity. To resolve these problems, two categories of phase modulators have become prominent which will be briefly explained.

2.2.1 Open Loop Phase Modulator

In open-loop modulation techniques, the modulation does not involve any PLL loop. It isolates a frequency generation circuitry from a data modulation circuitry, resulting in a modulator which does not involve the loop filter. Hence, these modulators can handle wide bandwidth. In a typical open-loop phase modulator, there is a phase generator circuitry which produces different phases at

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the carrier frequency. It is followed by a multiplexer whereby output is controlled by the modulation data [8]. This approach suffers from phase quantization noise, nonlinearity of digital to phase converter, and spectral images. Another approach consists of delay-based phase modulators capable of dynamically delaying the local oscillator edges every period. However, it requires a glitch-free phase MUX to facilitate managing the phase jumps as well as phase unwrapping for achieving wideband operation [9].

2.2.2 Closed-loop Phase Modulator

By adding a phase locked loop (PLL) around the VCO, carrier frequency is tightly controlled. In this case, modulation data has been successfully applied to the PLL employing a multi-modulus feedback divider in a fractional-N PLL [10]. However, high frequency content of the modulation data will be filtered out, subsequently limiting this application to narrow band applications. Bandwidth enhancement methods such as phase noise cancellation, type I fractional-N PLL and digital pre-emphasis can be applied; however, they cannot achieve very high bandwidth.

Wide loop bandwidth PLLs have the advantages of 1- fast channel switching; 2- better pulling immunity; and 3- filtering out the close-in flicker phase noise of the digitally controlled oscillator (DCO) which can be the dominant contribution in the scaled CMOS. However, the larger the bandwidth, the lower the attenuation of the loop filter on noise and spurs induced by the other input blocks [11]. In order to increase the bandwidth beyond the loop bandwidth of the PLL, the technique two-point modulation has been utilized [12,13] by simultaneously injecting the modulation data at the nodes of PLL loop with either high-pass or low-pass transfer function such that the overall of the two transfer functions becomes flat and wideband.

Using analog PLL is not desirable in scaled CMOS processes due to its performance degradation. For instance, the value of the charge-pump current cannot scale down because, first, it is set by the noise constraint and, secondly, the quality of the charge-pump current generators degrades as the voltage supply scales down. Moreover, the area occupied by the loop filter does not scale, and as a result, the filter may be very bulky. In some cases, it must be realized by employing external components, and it cannot be easily programmed to control the PLL bandwidth. Spur-cancellation algorithms, such as those based on correlation, must be applied to analog variables relying on analog blocks. This technique, however, increases the power consumption and provides limited cancellation [11].

The development of an all-digital PLL (ADPLL) [13] has afforded new possibilities for accom-plishing high resolution phase modulation. In this case, digital data can be readily introduced at most of the internal nodes of the PLL. In the next section, we further discuss this type of modulator in detail.

2.3 Building Block of the Digital PLL-base Transmitter

Fig. 2.2 depicts top level block diagram of the typical ADPLL-based transmitter system, which will be discussed in detail in a following subsections. As previously mentioned, using digital

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2.3 Building Block of the Digital PLL-base Transmitter 11 CORDIC SCS FCW limiting

I

up

Q

up SRC DBB

I

m

Q

m CKVD CKVD CLK CKS Exception Handling Differentiation FM Processing Unit CKVD

N

frac

CKVD CKS µ µ

Swapper

Swapping Indication Swapping Indication

f

DCC

Frac

Divider

Cal. Cal.

f

Pulse shaping & Upsampling CLK

I

k

Q

k Fref TDC DCO

ADPLL

Figure 2.2: Block diagram of transmitter phase modulator based on an ADPLL. techniques

• Allows calibrating and canceling of quantization noise and reduce in-band noise;

• Allows using techniques such as dynamic element matching (DEM) to alleviate sensitivity to component mismatches;

• Permits reconfigurable RF front-end to meet the requirements for multi-standard wireless com-munication;

• Eases porting the design from one technology node to the next and benefits from process scaling; • Enables to use calibration algorithms and state machines to correct for transmitter impairments

such as nonlinearity, PVT variations.

Although digital techniques may reduce quantization noise, PVT variation, nonlinearity, and the power consumption of the front-end, still require optimization and careful attention. [11].

2.3.1 Time-to-Digital Converter (TDC)

TDCs have been used for more than last two decades in various fields where precise time-interval measurement is required. All-digital PLL is the first and most famous TDC application that rapidly emerged. There are different types of TDC which basically have a trade off between the resolution, power, and input range. The basic structure, i.e., the flash TDC, is illustrated in Fig. 2.3. The

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Thermometer Code decoder DCO Clock Reference Clock Out DCO Clock Reference Clock Q Out 00111100 6 Q(1) Q(n) D(1) D(n) td

Figure 2.3: Simplest time to digital converter.

Differential switch-cap sw itc h -c ap sw it ch -c ap Fine Coarse

Unit/Binary Element Array

Figure 2.4: Coarse and fine control segmentation of the DCO.

resolution then depends on the delay elements (e.g., inverter) in the chain which is typically 10 ps for 40 nm CMOS process. This structure is very simple with low latency, however, TDC resolution is limited to the technology process. In [14] a pseudo-differential architecture is introduced that is insensitive to NMOS and PMOS mismatches with the same resolution as the flash TDC. One way to improve the resolution is by utilizing a Vernier delay line [15] that uses two long delay lines. The first delay line has a delay t_d1 which is slightly larger than the delay t_d2 of the elements in the second chain. This structure can achieve very fine resolutions smaller than an inverter delay at the cost of higher power consumption. Another technique to achieve higher resolution is a so called local passive time interpolation [16]. It has a differential delay line and the same latency as basic TDC but with increased resolution by using linear interpolation employing resistors. Time amplification is another approach which is a two-step (coarse-fine) approach. First, a coarse TDC is used to estimate where the signal is and a fine TDC is subsequently placed ’around’ the coarse estimate for improved accuracy [17]. However, the gain of the timing amplifier is very sensitive to PVT variation and requires intensive calibration. A Gated Ring Oscillator (GRO) is another effective method to improve resolution well below an inverter delay by virtue of the noise shaping that it offers [18]. There are additional TDCs which are less attractive for industrial purposes such as time window TDC [19], stochastic TDC [20], and 2D-Vernier TDC [21].

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2.3 Building Block of the Digital PLL-base Transmitter 13 Rb Rb Ctune Ctune B0 Ctune Ctune B0 B0

Figure 2.5: Two common differential structures for frequency tuning in the DCO.

α

IIR IIR IIR IIR

ρ Z-1 1-Z-1

Figure 2.6: Loop filter with single-pole IIR stages and an accumulator that provides a pole at dc.

2.3.2 Digitally Controlled Oscillator (DCO)

A digitally controlled oscillator (DCO) was used to perform the digital-to-frequency conversion (DFC), which avoids any analog tuning controls, and was first introduced in [22] for RF wireless applications. In a conventional voltage controlled oscillator in a scaled CMOS, the frequency tuning of a VCO has variable gain that have an effect on the PLL stability, and phase noise, due to the nonlinear voltage dependent capacitance of an MOS varactor. It uses a DAC to control the oscillator frequency. DCO mitigates these problems, by splitting the capacitance into digitally controlled tuning capacitors (see Fig. 2.4). Their bits individually control capacitative states of the LC-tank varactors, thus establishing the LC-tank resonating frequency. Normally, the capacitance split into process-voltage-temperature banks (PVT) and acquisition banks, respectively, which are activated sequentially during frequency locking and are frozen afterwards. Note that it is not easy to freeze the voltage in VCOs. The main way to calibrate the frequency in a DCO is by using switched capacitor circuits (see Fig. 2.5). During the on-state, the gate of the switch is V_DD, and its drain and source terminals are biased to ground via either resistor or transistor. The capacitance (Ctune)

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2.3.3 Loop Filters

One of the primary issues with analog PLL is the loop filter capacitances which have leakage current and consume large area. Due to the nature of the ADPLL, the signal inside of the loop is digital which leads to efficient and compact implementation of the loop filter. A sample digital loop filter is shown in Fig. 2.6. This has a second pole at zero frequency, thus producing a type II ADPLL. A significant advantage of type II topology is its better filtering capabilities of oscillator noise which result in improvements in the overall phase-noise performance. Both proportional and integral coefficient are implemented in an effective manner as right-bit-shift operations. Digital nature provides the capability of increasing the order of the loop filter by inserting cascaded single-pole IIR stages and superior filtering compared to its analog counterpart.

2.3.4 Upsampling Chain

Every transmitter includes a digital upconversion circuitry. This contains a pulse shaping filter which is used to upsample the I and Q signals and smoothes the transitions when progressing from one constellation point to another, thus restricting the complex signal spectrum to a bounded bandwidth. The shape of the filter is defined by the standard. The sampling frequency of the filter, the length of the filter, and coefficient quantization are determined for the individual design based on the margin desired over the specifications, which will be discussed later. The process of the sampling generates spectral image which can violate the standard mask specifications thereby increasing the baseband sample rate is desirable. This would place the image at an extensive distance and hopefully filter out by the low pass nature of the system.

There are different types of filters, which can be used in the upsampling path. One group is the finite impulse response (FIR) filter, that is inherently stable. The filter order should be high enough to provide good filtering. The infinite impulse response (IIR) filter is another type of filter with internal feedback that can lead to instability. The only genuine advantage of an IIR filter is that the required filter order is minimal. However, coefficient quantization and the implementation is more complicated because of the feedback and the fact that it is prone to limit cycles. The other filter is a cascaded integrator comb (CIC). The CIC filter is a multiplier-free filter that requires limited storage, which is very desirable from an economical perspective and does not require any storage for the filter coefficients. This filter has an undesired passband droop which often leads to the use of a conventional FIR filter for compensation.

There are filters referred to as the Nyquist filters or Lth-band filters [23], which are often used in single-rate and multi-rate signal processing. they have an attractive property whereby approximately 50% of the coefficients are zero (an Lth-band filter for L = 2 is called a half-band filter). This significantly reduces the number of multiplications required in its implementation. For example, if

N = 101, an arbitrary type I FIR transfer function requires about 50 multipliers, whereas a type I

half-band filter requires only about 25 multipliers. Lth-band filters can be either FIR or IIR filters. Digital filters have several advantages with respect to the analog filters. They have relatively high accuracy and linear phase (FIR filters). They have no drift due to component variations and facilitate adaptive filtering. Finally they are easy to simulate and design. However, they also require

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2.4 System Level Specifications 15

high performance ADCs, DACs and DSPs.

2.4 System Level Specifications

The RF transmitter dynamic performance is subsequently divided into in-band performance and out-of-band spectral purity. The error vector magnitude (EVM) is conventionally utilized for the evaluation of the in-band performance. In a transmitter, EVM could be affected by non-idealities such as upconversion mixer I/Q mismatch, LO phase noise, I/Q channel mismatches and, carrier leakage. The EVM is defined as the root-mean-square (RMS) of the error between the measured symbols sn and the ideal ones sr and is expressed as [24]:

EVM_RMS = v u u t N X i=1 1 N × (sr(i) − sn(i)) 2 v u u t N X i=1 1 N× (sr(i)) 2 (2.1)

where N is the number of iterations for each point. Additionally, the out-of-band spectral purity can be evaluated as an adjacent channel leakage ratio (ACLR) and far-out noise performance at the corresponding receiver frequency band of interest. ACLR is utilized to measure the nonlinear distortion in the transmitted signal. Moreover, ACLR in combination with the modulation scheme determines the maximum allowable nonlinearity of the related RF transmitter. ACLR is defined as follows [25]:

ACLR_adj= Padj

P_main (2.2)

where Padj is the total adjacent right/left channel power, and Pmainis the total RF power within the

main transmit channel. Note that, instead of ACLR, the third order intermodulation product (IM3)

can also be employed [25]. Furthermore, as will be discussed later, the far-out noise performance of the RF transmitter strongly depends on quantization noise and baseband upsampling rate. In this aspect, we investigate the effect of non-ideality and impairment in a transmitter in the context of the merits mentioned above.

2.4.1 Far-out Noise Floor

Each transmitter emits certain amount of noise which seriously degrades reception at the receiver. In a cellular communication standard, a transmitted noise level of -79 dBm at the corresponding receive-band is specified so as not to desensitize a nearby receiving mobile handset, measured with a 100 kHz resolution bandwidth (RBW). This situation is illustrated in Fig. 2.7 for a GSM case.

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880

915

20 MHz

935

960 MHz

+33 dBm

GSM TX GSM RX -79 dBm

Figure 2.7: Noise from transmitter into the receive band.

This corresponds to phase noise of -162 dBc/Hz at a offset frequency of 20 MHz with a power level of +33 dBm.

For a 3G transmitter, requirements come from a duplexer isolation of 45 dB, and a receiver noise figure (e.g., with a 3 dB noise figure, hence the noise level is -174 dBm/Hz - 3 = 171 dBm/Hz). If the receiver can tolerate 0.5 dB noise figure degradation, then the total added noise from the transmitter should be -180 dBm/Hz. Hence, required phase noise by the transmitter at receive band can be calculated as:

PN = −180 dBm/Hz − (26 dBm − 45 dB) = −161 dBc/Hz. (2.4) Here, duplexer/switch loss is neglected, and the full power of 26 dBm at the antenna has been assumed. This signifies that the far-out phase noise should be in the order of -160 dBc/Hz. This extracted phase noise has placed limitation on the oscillator phase noise, related divider, and buffer design.

2.4.2 Signal Specification

As described earlier, an alternative to the I/Q topology is the polar realization in which the two uncorrelated, i.e., orthogonal, components (alternative to the I and Q components) are amplitude ρ and phase θ: ρ = q I2_{+ Q}2 θ = tan−1 _Q I (2.5)

The complex-envelope signal is S = ρ exp (jθ). The I and Q signal spectral content is limited to the channel bandwidth, which is the characteristic of a well contained signal that can be sampled with any frequency higher than twice the bandwidth without causing any loss of information, as explained by the Nyquist sampling theorem. After experiencing the Cartesian to polar conversion,

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2.4 System Level Specifications 17 -30 -20 -10 0 10 20 30 -180 -160 -140 -120 -100 -80 -60 -40 Frequency (MHz) PSD I  q

Figure 2.8: Bandwidth expansion of the WCDMA signal in polar transmitter.

-0.6 -0.4 -0.2 0 0.2 0.4 0.6 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 I Q (a) 0 50 100 150 -3 -2 -1 0 1 2 3 x 107 Fr eq u en cy ( Hz ) Time (µs) fs/2 fs/2 (b) -30 -20 -10 0 10 20 30 0 2000 4000 6000 8000 10000 12000 14000 16000 Frequency N u m b er o f o cc u ra n ce (c)

Figure 2.9: (a) A snapshot of the I/Q trajectory for WCDMA data; (b) frequency information with instantaneous large deviation; (c) distribution of the frequency deviation.

the resultant amplitude and phase signals are not utilizing the same bandwidth that is exploited by the I and Q signal (Fig. 2.8). Polar transmitter bandwidth expansion limits the use of polar architecture for some of the newer standards (e.g. WCDMA) using wider frequency modulation. For these standards, the rate of operation for I/Q to polar conversion and all of the modules that operate in polar coordinates becomes very high causing increased power consumption and bigger areas. Amount of the frequency change in the polar transmitter can be calculated as follows:

dθ dt = d dt tan−1 Q(t) I(t) (2.6) dθ dt = I · dQ/dt + Q · dI/dt I2_{+ Q}2 (2.7)

Equation (2.7) demonstrates that trajectories that fly by or through the origin of the I/Q plane result in the largest instantaneous frequency, i.e., the largest deviation from the nominal carrier frequency (Fig. 2.9). Modulation schemes with high PARs are more susceptible to produce trajectories that pass near the origin which result in large frequency deviation. This can be prevented with methods such as zero crossing avoidance pre-distortion [26,27]. According to Fig. 2.9c, although

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18 Transmitter Architecture Considerations r q I/ Q -to -p o la r co n ve rt e r I Q D ig it a l b a se b a n d ( D S P ) V a ri a b le b a n d w id th F IR fi lt e r r q C o m b in e a n d p u ri ty m e a su re m e n t EVM ACLR f f (a) 0 0.2 0.4 0.6 0.8 -120 -100 -80 -60 -40 -20 0 Normalized Frequency M ag n it u d e (dB ) 0 0.05 0.1 0.15 0.2 0.25 0.3 -2 -1 0 1 2 3 4 x 10-5 M ag n it u d e ( dB ) (b) 0 5 10 15 20 -90 -80 -70 -60 -50

Bandwidth Expansion Factor

M o d u la ti o n A c c u ra c y ( d B ) (c) 0 5 10 15 20 -70 -60 -50 -40 -30 -20

Bandwidth Expansion Factor

A C L R ( d B c ) (d)

Figure 2.10: Bandwidth expansion in a polar transmitter (a) simulation test setup; (b) variable bandwidth FIR filter; (c) measured signal accuracy versus bandwidth expansion factor; (b) measured ACLR 1 versus bandwidth expansion.

these frequency deviations very rarely occur (96% of the time WCDMA trajectory is sufficiently distant from the origin, and the resulting frequency modulation is contained in a very narrow band), however, the transmitter should ensure that not degrading of the spectral purity.

Fig. 2.10a shows a simulation setup developed in MATLAB to analyze the effect of the bandwidth expansion on the signal purity. Digital block generates a QPSK with a square-root-raised-cosine pulse shape filtering, similar to WCDMA without any spreading and scrambling. However, such expansion is normally considered to be approximately 10-15X of the original signal’s bandwidth [28,29]. After polar conversion, a high-order and linear-phase FIR filter with a maximally flat top and sharp passband to stopband transition is used; the response is shown in Fig. 2.10b. Fig. 2.10c and Fig. 2.10d illustrate the simulation results and show the effect of bandwidth expansion on the spectral purity of the signal. Therefore, it is easy to conclude that, after certain point (for example 10X) not much improvement is visible in the spectral purity of the output signal.

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2.4 System Level Specifications 19 44 th FIR 2 MUX 2 18 th FIR 2 MUX 2 10 th FIR 2 MUX 2

CLK

Input

Output

Figure 2.11: Block diagram of the digital interpolation filter.

2.4.3 Upsampling Chain

As mentioned previously, in designing the upsampling chain, digital FIR interpolation filters were employed to attenuate the images that were evidenced in the low-rate input data when they are up-sampled to a higher frequency. In designing the transmitter, the number of the bits for I/Q signal must be properly selected in order to avoid any SNR loss. The upsampling chain in the transmitter serves to increase the sample rate and it normally contains several interpolators by a factor of two. Fig. 2.11 depicts the block diagram of the digital interpolation filter. It consists of a cascade of three stages of FIR filters to provide an upsampling ratio of 8. Each stage is driven by a clock signal consequently divided from a clock. As an example, for the first stage, a 44th-order FIR filter is used which has a pass-band corner of 0.45 normalized sampling frequency. The pass band has a ripple less than 0.01 dB while the stop band provides around 75 dB attenuation. The filter transition band of later stages, since the frequency spacing between the signal band and the image becomes larger, can be relaxed, and the filter order can be reduced. The orders of the 2nd and 3rd FIR filter stages are designed to be 18th and 10th, respectively. As shown in this figure, a multiplexer was employed in each filter stage to ensure that the upsampling ratio is programmable. The magnitude response of each stage and the total cascaded filter are shown in Fig. 2.12. By using this chain, the generated image will attenuated sufficiently for a specific standard mask. Several simulations were performed which indicated that this has a negligible effect of approximately 0.05 % of the EVM and almost no effect on the ACLR of the signal with enough bit resolution (e.g., 14 bits).

The sampling rate selection for these filters is primarily driven by the placement of replicas. If this sampling frequency is selected to be small, increased numbers of replicas will be contained up to the carrier frequency. On the other hand, increasing this sampling frequency, increases the oversampling ratio thus increasing the number of filter coefficients and complexity.

One of the critical design parameters for the digital filter is the quantization of the filter. The internal bitwidth of the filter is optimized accordingly to ensure that the effective number of output bits are not limited by internal resolution at any point.

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20 Transmitter Architecture Considerations 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Normalized Frequency M ag ni tud e ( dB ) (a) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Normalized Frequency M ag ni tu de ( dB ) (b) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Normalized Frequency M ag ni tu de ( dB ) (c) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -140 -120 -100 -80 -60 -40 -20 0 Normalized Frequency M ag ni tu de ( dB ) (d)

Figure 2.12: Magnitude plot of the different stages of digital interpolation filter.

2.4.4 CORDIC

The Cartesian domain I/Q signals are converted to polar domain ρ/θ signals using COordinate Rotation DIgital Computer (CORDIC) module. CORDIC algorithms perform a wide range of functions such as trigonometric, hyperbolic, linear, and logarithmic functions without using a hardware multiplier. The algorithm uses a shift-and-add mechanism to perform these operations using a small lookup table (LUT) [30]. The conversion between the Cartesian and polar coordinates can be expressed by the non-linear equations as in (2.5).

The sampling frequency of CORDIC is also a critical system parameter. With any increase in sampling frequency, the need for a faster clock increases the power consumption of CORDIC. Similarly, the bitwidth at the output of CORDIC is another critical system design parameter.

There are three different architectures for implementing the CORDIC. The first is based on a look-up table (LUT), which is not suitable for high performance applications due to its low speed and power consumption. The second is based on the simple CORDIC unit and operating it iteratively

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2.4 System Level Specifications 21 -100 -50 0 50 100 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 Frequency (MHz) P SD ( dB )

Interpolation before CORDIC Interpolation after CORDIC

Figure 2.13: Effect of placing CORDIC before interpolation chain on the modulation spectrum.

Register >> i sign Register >> i Register tan-1(2-i) di di CORDIC unit Zi+1 Yi+1 Xi+1 X0 Xi Y0 Yi Z0 Zi (a) (b)

Figure 2.14: (a) block diagram of the CORDIC unite; (b) layout of the 14-bits resolution CORDIC in 40 nm CMOS technology (Size: 120µm × 120µm)

produce sufficient resolution, which is very efficient for low power and low-speed applications. Operating the CORDIC unit in a pipeline ensures suitability for high-speed applications. The block diagram of the CORDIC unit is illustrated in Fig. 2.14a. One important point is that the interaction between CORDIC and interpolation filtering must be taken into account. On one hand, if this conversion is performed prior to filtering, the CORDIC can run at a much slower speed. On the other hand, placing the CORDIC after the filter produces data that is more accurate since the filter performs linear operations on a linear version of the signal. Placing CORDIC before filtering imposes a limitation on modulation accuracy such as EVM and ACLR. An example of WCDMA

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22 Transmitter Architecture Considerations 0 0.5 1 1.5 2 2.5 3 3.5 4 5 10 15 20 25 30 35 40 SS TT FF Transistor width (µm) D ela y (ps ) 0 0.5 1 1.5 2 2.5 3 3.5 4 15 20 25 30 35 40 45 50 SS TT FF Transistor width (µm) C u rr en t con su m p ti o n ( µ w )

Figure 2.15: Delay and power trade off in TDC cell in different corners.

data is shown in Fig. 2.13. In this particular simulation, EVM degradation is approximately 0.2% with an enormous impact on ACLR. This situation exacerbates for wideband modulation and leads to the conclusion that, for emerging wideband standards, CORDIC should be placed after filtering.

To gain insight about the speed, size, and power consumption of a typical CORDIC, a piplined CORDIC is fully synthesized and place-and-routed in 40 nm CMOS technology, whose its layout is shown in Fig. 2.14b. In typical case scenario it can be operated at a maximum frequency of 1 GHz with a power consumption of 7.5 mW (from post place and rout synthesis). However, this sampling rate reduces in a worst case scenario (i.e. SS corner) to around 600 MHz.

2.4.5 TDC

It has been demonstrated in [31] that the TDC requirements arise primarily from the spurious emissions rather than from the phase noise or the RMS phase error specifications. As mentioned in Fig. 2.13, TDC is one of the most power consuming-blocks in ADPLL and often establishes the jitter/power trade-off. Therefore, any digital correction algorithm based on a high-resolution and/or high-linearity TDC could only minimally improve the jitter/power trade-off [1]. Fig. 2.15 shows the effect of the sizing on the power/delay of the inverter based TDC cells over the process corners. Moreover, distribution of the TDC resolution with a mismatch in the delay cell is shown in Fig. 2.16 for two different inverter’s transistors width. The TDC resolution has traditionally been associated with the loaded delay of the basic regenerative circuit, i.e., an inverter. With only 7-8 ps of inverter delay now in 28 nm CMOS, there are over 60 inverters required to cover the 2 GHz (i.e., cellular highband) DCO period. With each inverter introducing a small differential type of non-linearity (DNL), these nonlinearities can quickly accumulate to form a much larger integral type of non-linearity (INL) of the TDC transfer function. At the same time, new wireless standards require low in-band phase noise and spurious tones. With the improved TDC resolution, which lowers the in-band quantization noise and also improves the TDC transfer function nonlinearity

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2.4 System Level Specifications 23 9 9.5 10 10.5 11 11.5 12 12.5 13 0 20 40 60 80 100 120 Delay (ps) N u m b e r o f o cc u rr e n ce 6.5 7 7.5 8 8.5 9 9.5 10 0 20 40 60 80 100 120 Delay (ps) N u m b e r o f o cc u rr e n ce µ = 11 ps σ = 0.6 ps µ = 8.3 ps σ = 0.4 ps

Figure 2.16: Effect of mismatch on the TDC resolution for W = 1µm (left) and W = 2µm (right). which can create fractional spurs especially at close to integer-N channels or at wide loop bandwidth PLLs. In designing an ADPLL transmitter, the TDC effect is only on the EVM. A simple way to calculate EVM will be described here. According to [32], TDC with ∆t_inv resolution has a phase noise of: L = (2π) 2 12 _∆t inv T 2 · 1 fR (2.8) where T is the DCO clock period and fR is the sampling frequency. Substituting ∆tinv = 10 ps, fR= 40 M Hz, and T = 500 ps, we obtain L = −103 dBc/Hz. By calculating the area under the

phase noise plot, integrated phase noise (INP) is achieved (See Fig. 2.17).

INP = 10log(A1+ A2) (2.9)

PE = 180

π q

10INP10 (2.10)

where PE is RMS phase error in degree. It is easy to show that this only modulate the phase and, hence, the EVM is simply calculated as:

EVM = 2 sin(PE/2) (2.11)

As an example, the value calculated above for a bandwidth of 200 kHz leads to a 0.2% EVM degradation. It is obvious that the TDC is not the main contributor to the EVM, and the need for low resolution is, basically, to reduce the spurious tone generated from the TDC. Fig. 2.17 shows the main contributors to the phase noise at the output of the ADPLL transmitter. The inband phase noise is generally dominated by the TDC quantization noise since the reference noise is normally quite low. For improved jitter performance, the loop bandwidth should be optimized according to the flicker and thermal noise of the oscillator.

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24 Transmitter Architecture Considerations 0.01 0.1 1 10 -160 -150 -140 -130 -120 -110 -100 -90 -80 Frequency (MHz) O u tp u t p h a s e n o is e ( d B c /Hz ) Uncorrected DCO Reference TDC Variable (DCO) Composite A2 A1 fc

Figure 2.17: Effect of TDC, reference and the DCO noise at the RF output.

2.4.6 DCO

In an ADPLL-based transmitter, the DCO is one of the major blocks that limits the spectral purity. For a DCO design based on a differential LC oscillator core with a digitally adjustable varactor for fine tuning, the nonlinear behavior originates from the inherent relation between the resonating frequency and the capacitive tuning given by the root equation for a resonant LC circuit which considers as systematic errors. Besides, random fluctuations due to process, voltage and temperature (PVT) variations will have an impact on the DCO nonlinearity. It is well-known that feedback can alleviate nonlinearity, however, when modulating the ADPLL, the distortion due to the nonlinear transfer characteristic of the DCO can only be compensated within the PLL bandwidth. Frequency content outside of this PLL bandwidth will be deteriorated due to the DCO nonlinearity and is directly translated to the modulated output phase and affects the RF performance. The DCO, in this case, is known as a digital to frequency converter. This circuit has two important primary parameters: First the tuning range and, second, the modulation range. The tuning range is derived from process, voltage and temperature variation. However, modulation range depends on system parameters. In a digital transmitter, images at multiple sampling frequencies are inherently generated. Therefore, in order to meet the mask specifications of the standards, the sampling frequency normally needs to be increased as much as possible.

As shown in Fig. 2.9, when the I and Q signal trajectory passes through the origin, there can be an instantaneous phase change of π radians, which translates to a half sampling frequency change. If the sampling frequency of the CORDIC is fcor, then the instantaneous frequency change is

±π

2πfcor = ±fcor/2. Hence, the DCO should be able to manage these large instantaneous frequency requirements. This resulting frequency range requirement due to modulation is referred to as the modulation range. As a result, the modulation range of the DCO should be equal to fcor [33].

The modulation bandwidth related to a specific standard increase and, considering the bandwidth expansion and images, leads to increases in the sampling frequency of the CORDIC. For instance,

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2.4 System Level Specifications 25

to support a WLAN signal, the sampling frequency of the CORDIC and the DCO modulation range should be, for example, approximately 300-400 MHz (for proper frequency selection, extensive simulation must be conducted) [33]. For example, WLAN systems operate in 2.4 GHz as well as 4.8-5.9 GHz, this implies the DCO tuning range. Due to the need for a quadrature signal, the DCO must operate at twice and four times the carrier frequency for different bands of operation. Hence, it should have a tuning range of 9.6-11.8 GHz and also the modulation range requirement of 300-400 MHz at 2.4 GHz which translates to 1.2-1.6 GHz modulation range at 9.6 GHz. This is quite substantial. The modulation and tuning ranges of the DCO are very critical parameters. As the modulation range of the DCO increases, the number of capacitors required in the design also increases thereby increasing the parasitic capacitance, which makes it difficult to achieve a wide tuning range while providing the large modulation range for the DCO. Therefore, for practical implementation of these types of systems, the modulation range should be reduced with certain techniques.

One method to reduce the modulation range is an exception handling technique to manage the sudden phase jumps of π radians [33]. In this case, the output clock of the DCO is inverted to accommodate this jump. This method extremely complex as it is implemented in the analog domain by multiplexing the different phases of the DCO clock and hence can also potentially degrade the phase noise performance of the system. Accommodating more phases of the DCO clock such as π/n etc. where n is an integer increase the implementation complexity. Another approach is to disperse these big phase jumps over adjacent samples to modify the trajectory in such a way that the total accumulated phase maintains constant. This technique employs a specified threshold for phase jump and spreads the remaining phase. This redistribution of phase causes the resulting phase trajectory to deviate slightly from the ideal one. These two approaches are illustrated in Fig. 2.18. The exception handing technique is very sensitive to phase mismatch of the DCO clock output which can easily dominate the EVM and decrease the efficiency of this technique. Phase thresholding can also be applied for a narrow range of phase jumps, since big jumps must be dispersed over more samples.

In order to determine the system-level importance of the DCO, a set of simulations has been performed. A signal with a 5 MHz bandwidth is applied to the DCO with a 50 MHz modulation bandwidth. The modulation capacitance bank is quantized with a small capacitance to provide frequency resolution of the 1 kHz. As mentioned above, the DCO acts as a digital to frequency converter in which a digital to capacitance relationship is linear, but the capacitance to frequency conversion follows the nonlinear equation below:

f = 1

2πpL(C + ∆C) (2.12)

where ∆C represents the small capacitance changes for modulation. If the modulation range is small, this equation can be approximated linearly. Moreover, there would be a mismatch between these fine tuning capacitances. As shown in Fig. 2.19, three different cases are considered. As is evident, the inherent nonlinearity of this conversion has an enormous effect on the modulation

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DCO

Exception handling Phase mux Frequency Data n n+1 n-1 n+2 n-2 Frequency Threshold D D D D D

Frequency Threshold ALU

Frequency Data

Figure 2.18: Modulation range reduction techniques.

-25 -20 -15 -10 -5 0 5 10 15 20 25 -180 -160 -140 -120 -100 -80 -60 Frequency (MHz) P o w e r/ fr e q u e n c y ( dB /Hz )

Linear and Mismat ch Nonlinear

Nonlinear and Mismatch

(a) -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 I Q

Linear and Mismatch Nonlinear

Nonlinear and Mismatch

(b)

Figure 2.19: Effect of the DCO inherent nonlinearity and mismatch on the spectrum and the constellation.

accuracy, and this situation exacerbates with larger data bandwidth. In this case, by considering a 5% mismatch in each capacitance, the EVM degradation is extensive from 1.5% to 20% and ACLR degradation by approximately 10 dB. Fig. 2.20 quantifies both INL and DNL of the DFC. The problem that arises from the nonlinearity of the equation is that the would be negative frequency drift which is evident from the rotation of the constellation.

2.4.7 Baseband Sample Rate

Advanced wireless communications use Orthogonal Frequency Division Multiplexing (OFDM), which is one of the multi-carrier modulation techniques. This technique offer a considerable high spectral efficiency and multi-path delay spread tolerance. As a result, OFDM has been selected for

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2.4 System Level Specifications 27 0 1000 2000 3000 4000 5000 -20 -15 -10 -5 0 5 Code IN L ( L S B ) Only Mismatch Only Nonlinearity Nonlinearity and Mismatch

(a) 0 1000 2000 3000 4000 5000 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 Code D N L ( L S B ) On ly Mismat ch On ly Nonlinearity Non linearit y an d Mismatch

(b)

Figure 2.20: Effect of the DCO inherent nonlinearity and mismatch on the INL and DNL of the DFC.

high data rate communications and has been widely used in many wireless communication standards such as mobile WiMAX. However, this spectral efficiency comes at the cost of high Peak-to-Average Power Ratio (PAPR) compared to a single carrier signal. Hence, OFDM signal requires linear power amplifier, where the power conversion is inefficient. This may have a negative effect on the battery lifetime in portable mobile devices, where the drawback of high PAPR may outweigh all the potential benefits of OFDM.

The PAR is defined in [34], which provides information on how the signal is distributed over the amplitude range. A low PAR indicates a more uniform distribution, which is advantageous in most cases. The PAR can be calculated as [34]:

PAR = Peak Amplitude

rms Value (2.13)

For a sinusoidal signal PAR = √

2. For an N-bit converter, the signal to noise ratio can be calculated from [34]:

SNR = 6.02N + 4.77 − 20log(PAR) (2.14)

As mentioned before, in a digital transmitter baseband sample rate, is a critical parameter in a design. This sample rate also has an effect on far out noise, which we briefly elaborate on (see Fig. 2.21). SNR = 10 log(Psignal P_noise) (2.15) P_signal= A_signal× BW RBW (2.16) Pnoise= Anoise× fs RBW (2.17)

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28 Transmitter Architecture Considerations 0

_f

_s

_/2

Frequency P S D

-f

s

/2

BW

A

signal

A

noise

SNR = 10log(Psignal/Pnoise)

Psignal = Asignal× (BW/RBW)

Pnoise = Anoise× (fs/RBW)

Figure 2.21: A sample snapshot of the output spectrum of the transmitter. From the above equations and (2.14), The following simple equation can be evaluated.

10 log(Psignal

P_noise) = 6N + 1.76 + 10 log( fs

BW) (2.18)

10 log(RBW) = 10 log(A_signal) + 10 log(BW) − 10 log(p_signal) (2.19) 10 log(Pnoise) = 10 log(Anoise) + 10 log(fs) − 10 log(Asignal) (2.20)

whereby RBW is the resolution bandwidth. After some simplifications, noise floor can be derived: Noise floor = 10 log(P_signal) − 10 log(fs) − 6N − 1.76 (2.21) where 10 log(P_noise) = Noise floor + 10 log(f_s). As an example, consider a digital transmitter with 13 bits resolution, baseband sample rate of 300 MHz, and output power 23 dBm. The noise floor from (2.21) then evaluates as -141.5 dBm/Hz. This substantiates that baseband sample rate has a significant effect on the far out noise of the transmitter. Moreover, PAR can also degrade this per (2.14).

2.4.8 Oscillator Pulling

In today’s integrated wireless systems, especially in multi-standard applications (for example see Fig. 1.2), it is common that two or more PLLs are integrated on the same substrate and operate concurrently. Due to the limited isolations established by the substrate and package, the oscillators experience mutual interactions. The pulling interactions between two oscillators generates spurs in the spectrum and degrades the spectral purity of the entire transceiver. Specifically, local oscillator pulling is a critical bottleneck for direct-conversion transmitters. Frequency modulation interference that originates from the transmitter output signal often deteriorates the oscillator phase noise performance and hence worsens the quality of the transmission signal through a coupling to the oscillator. several works have attempted to mitigate the pulling effect which will be explained thoroughly in the next chapter.

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2.5 Conclusion 29

2.4.9 Other Non-ideality in an ADPLL-base Transmitter

As mentioned previously, this type of transmitter acts as a DAC. In [35] has been demonstrated that, in the RF domain, the two point ADPLL-based phase modulator functions as a reconstruction filter equivalent to a linear (or first-order) interpolator with delay. However, two paths must match precisely from a timing perspective and path gain to provide a flat transfer function. One other important aspect of ADPLL-based transmitter is that the sampling frequency employed for the digital logic is the data modulated clock output of the DCO and not a uniform constant clock. For low signal bandwidth systems such as GSM and Bluetooth, using the modulated clock for sampling does not affect the performance of the system. However, for large signal bandwidths, sampling with a modulated clock without any compensation is not possible and creates a significant drift in the samples in one direction as compared to samples generated with a uniform clock. Hence, another critical block is required, which is referred to as a variable fractional sample rate converter, in between. This must be implemented in an efficient manner and its sample rate ratio should be carefully selected.

2.5 Conclusion

In this chapter a brief overview, background material and design considerations for the modern digital transmitters were provided. An efficient method was discussed for implementing a phase modulator which would be suitable for high efficiency polar or outphasing transmitters. Several reasons signified above include moving with scaling and using digital and digitally assisted design as a must. Based on this fact, an all-digital PLL based transmitter was discussed as a potential solution. The primary building blocks of the transmitter were discussed, and it became more obvious that the DCO is the most critical building block that limits the spectral purity. As explained, integration is the main driving force for cost reduction, however this imposes many coupling issues for different parts of the transceiver, such as the local oscillator. This problem, as discussed, known as pulling, which will likely be the main cause degrading spectral purity of the TX output in multi radio SoCs. One major issue arises from taking advantage of a high-efficiency transmitter such as polar and outphasing is bandwidth expansion. Moreover, digitally intensive transmitters generate spectral replicas at multiples of the sample rate which could violate spectral mask. In addition, the noise floor of the transmitter could be affected by the sampling frequency. As a result, the system sample rate should be high enough to avoid the above mentioned issues. However, a high sample rate, as discussed, demands a wide linear modulation range for the DCO. This is not an easy task since there is inherent nonlinearity in digital to frequency conversion inside the DCO. Moreover, this high sample rate also increases the design effort of CORDIC. Another specification emerges from the noise in the receive band and, in the case of the DCO, the quantization noise plays role and the DCO must be carefully design due to the limited frequency resolution. Reduction of the magnetic field emission to other parts and the need for quadrature signals are two additional important parameters in designing the oscillator. Based on the above discussions, we will design a variety of oscillators in the following chapters to address the previously mentioned issues.

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Design of RF Oscillators for Wireless Digital Transmitters

Design of RF Oscillators for Wireless

Digital Transmitters

Design of RF Oscillators for Wireless

Digital Transmitters

Contents

C h a p t e r

1

Introduction

1.1

Is Analog/RF Doomed to Digitization?

CMOS node

Per

fr

o

ma

n

ce

/Ca

p

a

b

ili

ty

1.2

Aim and Scope

1.3

Original Contributions

1.4

Thesis Organization

C h a p t e r

2

Transmitter Architecture Considerations

2.1

Digital Transmitter Architectures

C

o

m

p

le

xi

ty

Efficiency

2.2

Phase Modulator

2.3

Building Block of the Digital PLL-base Transmitter

I

Q

I

Q

N

frac

Swapper

f

DCC

Frac

Divider

f

I

Q

ADPLL

α

2.4

System Level Specifications

880

915

935

960

MHz

+33 dBm

CLK

Input

Output

DCO

f

/2

-f

/2

BW

_f

_/2