BH7659FS

(1)

Input selector for high resolution displays

BH7659S / BH7659FS

The BH7659S / BH7659FS are input signal switching ICs developed for high resolution displays that have three fc = 250MHz wide-band video switching circuits for RGB video signal switching and four CMOS analog switching circuits for switching between H

D

and V

D

signals as well as I

²

C bus signals (SDA and SCL).

z z z

zApplications

High-resolution displays and high-definition TVs

z z z

zFeatures

1) Operates with a 5V power supply voltage.

2) Built-in, wide-band switching circuit for RGB switching (fc = 250MHz).

3) SDA and SCL as well as H

D

and V

D

signal switching is possible.

4) Built-in power save function.

z z z

zAbsolute maximum ratings (Ta = 25

°

C)

Parameter Symbol Limits Unit

Operating temperature Storage temperature

Topr Tstg

1300^∗1(SDIP32) 800^∗2(SSOP−A32)

°C

∗

1 Reduced by 13mW for each increase in Ta of 1˚C over 25˚C.

∗

2 Reduced by 8.0mW for each increase in Ta of 1˚C over 25 ˚C.

– 25 ~ + 75 – 55 ~ + 125 Power dissipation Pd

Power supply voltage VCC 8.0 V

mW

z z z

zRecommended operating conditions (Ta = 25

°

C)

Parameter Symbol Min. Typ. Max. Unit

Operating power supply voltage VCC 4.5 5.0 5.5 V Not designed for radiation resistance.

(2)

z z z

zBlock diagram

R A

B

A

B

A

A B

B

B G

B

POWER SAVE RINA

RGND

GINA

GGND

BINA

BGND

RINB

PSH

GINB

VDD

BINB

N.C.

CTL

VDINA

VDINB

VDOUT

RVCC

ROUT

GVCC

GOUT

BVCC

BOUT

HDOUT

HDINA

HDINB

SCLIO

SCLIOA

N.C.

SCLIOB

SDAIOA

SDAIOB

SDAIO CTL

A

B 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

(3)

z z z

zInput / Output equivalent circuits

VCC

2k 500

3.7V 10k

2k

VCC

50k

3.25V

Pin No. Pin description (pin name)

Reference

potential Input / output circuit Function

1

3

5

7

9

11

Switches between the two RGB signaling systems.

Input B is selected by setting the CTL pin to high and input A to low.

Power save activates by setting the PSH pin to high.

PSHPower save off ≤ 1.5V Power save on ≥ 3.5V CTLInput A ≥ 3.5V Input B ≤ 1.5V Red signal input A

(RINA)

Green signal input A (GINA)

Blue signal input A (BINA)

Red signal input B (RINB)

Green signal input B (GINB)

Blue signal input B (BINB)

27

29

31

Blue signal output (BOUT)

Green signal output (GOUT)

Red signal output (ROUT)

3.5V when selected

0V when not selected8

1.85V

8

9

Power save input (PSH)

Control input (CTL)

0V

(4)

VDD

OUT IN

Pin No. Pin description (pin name)

Reference

potential Input / output circuit Function

14

15

16

17

18

19

20

22

24

25

26

27

2

4

6

10

28

30

32

Switches between the two VD, HD, SDA, and SCL signaling systems.

Input B is selected by setting the CTL pin to high and input A to low.

Bi-directional I / O is possible with CMOS analog switch

Red video SW block GND

Green video SW block GND

Blue video SW block and CMOS SW block GND

CMOS SW block VDD

Blue video SW block VCC

Green video SW block VCC

Red video SW block VCC

VD signal input A (VDINA) VD signal input B (VDINB) VD signal output (VDOUT)

SDA signal I / O (SDAIO)

SDA signal I / O B (SDAIOB) SDA signal I / O A (SDAIOA)

SCL signal I / O B (SCLIOB) SCL signal I / O A (SCLIOA) SCL signal I / O (SCLIO)

HD signal input B (HDINB) HD signal input A (HDINA) HD signal output (HDOUT)

Red ground (RGND)

Green ground (GGND)

Blue ground (BGND)

CMOS power supply voltage (VDD)

Blue power supply voltage (BVCC)

Green power supply voltage (GVCC)

Red power supply voltage (RVCC)

0V

5V

5V 0V

—

(5)

z z z

zElectrical characteristics (unless otherwise noted, V

^CC

=5.0V, Ta = 25

°

C)

Parameter Symbol Min. Typ. Max. Unit Conditions

—

— Circuit current

Circuit current during power save

Voltage gain

Interchannel relative gain Interblock relative gain Output dynamic range

On-resistance

Interchannel on-resistance difference Interchannel crosstalk

Transmission delay time

High level voltage Low level voltage

ICC

IPSV

GV

VOM

RON

CT tD

VH

VL

15 7

– 1.0 – 0.5 – 0.5 2.6

—

3.5

—

25 14

– 0.5 0 0

—

200 20 – 70

20

—

〈Overall device〉

〈R, G, and B video switches〉

〈CMOS analog switch〉

〈Control block〉

35 22

0 0.5 0.5

—

400 40 – 55

—

— 1.5

mA mA

dB dB dB VP-P

Ω Ω dB ns

V V

PS = “H”

f = 10MHz f = 10MHz f = 10MHz f = 1kHz

VIN = 2.5V VIN = 2.5V f = 150kHz

RL = 10Ω, CL = 50pF

∆GVC

∆GVB

∆RON

z z z

zGuaranteed design parameters (unless otherwise noted, V

CC

=5.0V, Ta = 25

°

C)

Parameter Symbol Min. Typ. Max. Unit Conditions

Frequency characteristics 1 Frequency characteristics 2

Interchannel crosstalk 1 Interchannel crosstalk 2 Interblock crosstalk 1 Interblock crosstalk 2

Interchannel relative frequency characteristics

Interblock relative frequency characteristics

f1

f2

– 3.0 – 6.0

0 – 3

〈R, G, and B video switches〉

+ 1.0 – 1.0

dB dB

f = 50MHz f = 250MHz

CTC1

CTC2

CTB1

CTB2

—

– 50 – 30 – 50 – 30

– 35 – 15 – 35 – 15

dB dB dB dB

f = 50MHz f = 250MHz f = 50MHz f = 250MHz

∆fC

∆fB

– 0.5

– 0.5 0

0

0.5

0.5 dB

dB

f = 50MHz

(6)

z z z

zMeasurement circuit 1

+ V

C2

SW23 C1

+ V

C2 C1

+ V

C2 C2

1 SW1

2 C1

C1 = 0.01µF C2 = 47µF C3 = 50pF R1 = 75Ω R2 = 10kΩ V1 = 1.5V V2 = 3.5V C1

+

C2 1

SW3 2

C1

+

C2 R1 1

OSC1

SW5 2

C1

+

C2 1

SW7

SW8 2

C1

V1 V2 1 2

+

C2 1

SW9 2

C1

+

C1

+

C2 C2

N. C.

1 SW11 2

C1

+

A VCC AM

SW13

SW16

Fig.1

V2 V1 1 2 C1

C2

2.5V 1 2 3 SW14 R1 V3

+

OSC2

C1 C2

2.5V 1 2

3 1

2

3 R1 SW15

V3

+

C3 R2 OSC2

VV

1 2 3

R C3

VV

SW23

1 2 3

R C3

VV

2.5V

1 2 SW24 3R1

V3 C2

+

OSC2

2.5V

1 2 SW22 3

N. C.

R1 V3 C2

+

OSC2

2.5V

1 2 SW20 3R1

V3 C2 C1

+

OSC2

2.5V

1 2 SW25 3R1

V3 C2 C1

+

OSC2

SW17

1 2 3

R C3

VV

2.5V

1 2 SW18 3R1

V3 C2 C1

+

OSC2

2.5V

1 2 SW19 3R1

V3 C2 C1

+

OSC2 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

(7)

z z z

zMeasurement circuit 2

V

Ro

+

C2 C1

+ V

C2 C1

+ V

C2

R1 C2 C1

Ro

C1 = 0.01µF C2 = 47µF R1 = 50Ω Ro = 130Ω C1

+

OSC

N. C. N. C.

Ro R1 C2

C1

+

OSC

R1 C2 C1

+

OSC

R1 C2 C1

+

OSC

R1 C2 C1

+

C2 C1

+

OSC

R1 C2 C1

+

OSC A

VCC

VCC AM

1

IN: B CTL IN: A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

Fig.2

(8)

z z z

zMeasurement conditions

<Overall device> measurement circuit 1

Parameter Switch conditions

Others Circuit current

Circuit during power save

8 1 2

(1) (2) 1

1

Notes

<R, G, and B video switches> measurement circuit 2

Parameter Input pin: (OSC) Switch conditions

CTL Notes

Voltage gain (GV) Output dynamic range (VOM)

Frequency characteristics 1 (f1)

Frequency characteristics 2 (f2) Interchannel

crosstalk 1 (CTC1) Interchannel crosstalk 2 (CTC2) Interblock crosstalk 1 (CTB1) Interblock crosstalk 2 (CTB2)

Interchannel relative gain: ∆G^VC Interblock relative gain: ∆G^VB

Interchannel relative frequency characteristics: ∆fC

Interblock relative frequency characteristics: ∆f^B RinA RinB GinA GinB BinA BinB RinA→B RinB→A GinA→B GinB→A BinA→B BinB→A G→RinA B→RinA R→GinA B→GinA R→BinA G→BinA

1

—

— 7

—

— 3

—

— 9

—

— 5

—

— 11

—

IN: A IN: B IN: A IN: B IN: A IN: B IN: B IN: A IN: B IN: A IN: B IN: A IN: A IN: A IN: A IN: A IN: A IN: A

(3)

(8) (11)

(12)

(13)

(14)

(4) (5) (9) (10)

(6)

(7)

(9)

<C-ROM analog switch> measurement circuit 1

Parameter Switch conditions

Notes

On-resistance (RON)

Interchannel crosstalk (CT)

Transmission delay time (tD)

Interchannel on-resistance difference (∆R^ON) VDinA

VDinB SDinA SDinB SCinA SCinB HDinA HDinB VDinA→B VDinB→A SDinA→B SDinB→A SCinA→B SCinB→A HDinA→B HDinB→A VDinA VDinB SDinA SDinB SCinA SCinB HDinA HDinB

13 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

14 2 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1

15 1 2 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 3 1 1 1 1 1 1

16 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 1 1 1 1 1 1

17 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 1 1 1 1

18 1 1 1 2 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 3 1 1 1 1

19 1 1 2 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 3 1 1 1 1 1

20 1 1 1 1 1 2 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 3 1 1

22 1 1 1 1 2 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 3 1 1 1

23 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 1 1

24 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 3

25 1 1 1 1 1 1 2 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 3 1

26 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3

others 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

(15)

(17)

(18)

(16)

Notes:

(1) Circuit current : Icc ; measurement of the circuit current.

(2) Circuit current during power save : IPSV ; measurement of the circuit current during power save.

(3) Voltage gain : GV

VIN = 1.0VP-P, f = 10MHz sine wave input from the OSC GV = 20log (VOUT / VIN) [ dB ]

(4) Interchannel relative gain : ✁GVC

✁GVC = GVRa – GVRb, GVGa – GVGb, GVBa – GVBb [ dB ] (5) Interblock relative gain : ✁GVB

✁GVBR= GVRa – GVGa, GVRa – GVGb, GVRa – GVBa, GVRa – GVBb [ dB ]

✁GVBG= GVGa – GVRa, GVGa – GVRb, GVGa – GVBa, GVGa – GVBb [ dB ]

✁GVBB = GVBa – GVRa, GVBa – GVRb, GVBa – GVGa, GVBa – GVBb [ dB ] (6) Output dynamic range : VOM

Connect a distortion meter to the output. After adding a f = 1kHz sine wave input from the OSC, adjust the input level so that the output distortion is 1.0%.

The output voltage at that time is VOM [VP-P].

(7) Frequency characteristics 1 : f1

Apply to the input pin a VIN = 1.0VP-P, f = 10MHz and 50MHz sine wave input from the OSC.

f1 = GV (50MHz) – GV (10MHz) [ dB ]

(10)

(8) Frequency characteristics 2 : f2

Apply to the input pin a VIN = 1.0VP-P, f = 10MHz and 250MHz sine wave input from the OSC.

f2 = GV (250MHz) – GV (10MHz) [ dB ] (9) Interchannel relative frequency characteristics : ✁fc

✁fc = f1 (INA) – f1 (INB) [ dB ] (10) Interblock relative frequency characteristics : ✁fb

✁fb = f1 (RINA) – f1 (GINA), f1 (GINA) – f1 (BINA), f1 (BINA) – f1 (RINA) [ dB ] = f1 (RINB) – f1 (GINB), f1 (GINB) – f1 (BINB), f1 (BINB) – f1 (RINB) [ dB ] (11) Interchannel crosstalk 1 : CTC1

Apply to the input pin a VIN = 1.0VP-P, f = 50MHz sine wave input from the OSC.

CTC1 = 20log (VOUT / VIN) [ dB ] (12) Interchannel crosstalk 2 : CTC2

CTC2 = 20log (VOUT / VIN) [ dB ] (13) Interblock crosstalk 1 : CTBB1

CTB1 = 20log (VOUT / VIN) [ dB ] (14) Interblock crosstalk 2 : CTB2

CTB2 = 20log (VOUT / VIN) [ dB ] (15) On-resistance : RON

✁R^ON = (VOUT / VIN – 1) × 10⁴[ Ω ] (16) Interchannel on-resistance difference : ✁RON

✁RON = RON (INA) – RON (INB) (17) Interchannel crosstalk : CT

Apply to the input pin a VIN = 1.0VP-P, f = 150MHz sine wave input from the OSC2.

CT = 20log (VOUT / VIN) [ dB ] (18) Transmission delay time : tD

Apply to the input pin the rectangular wave of P1 from the OSC2.

100ns

tD

20ns VCC

0V

Output Input: P1

f = 150kHz

50%

(11)

z z z

zApplication example

SCL IO VCC

+ C2 C1

Ro

R3

R3 SDA IO

V^CC R OUT

G OUT

B OUT HD OUT +

C2 C1

VCC

+ C2 C1 R

G A

A

B B

A

B

A

B

A

A A

B B

B

+

C2 R1

R4 5. 1

Input A R G B VD

SDA

SCA

HD

Input B R G B VD

SDA

SCA

HD

R2 C1 VCC

+

C2 R1

R2 C1 VCC

+

C2 R1

R2 C1 VCC

+

C2

C3 R1

R2

R4 PS:H

C1 VCC

C2

R1 R2

C1 VCC

C2 R1

R2

R4

R3

VD OUT R3 C3 CTL

IN A: H IN B: L

N. C. N. C.

C1

C1 VCC

VCC

R4 5. 1

POWER SAVE

CTL 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

+

Note: The Ro value differs depending on the load capacitance.

Set so that the frequency characteristics are flat.

R1 = 75Ω C1 = 0.01µF R2 = 47Ω C1 = 47µF R3 = 100Ω C1 = 0.1µF R4 = 1.2kΩ

Fig.3

(12)

z z z

zExternal dimensions (Units : mm)

SDIP32 SSOP−A32

BH7659S BH7659FS

4.7 ± 0.3 0.51Min. 8.4 ± 0.3

3.2 ± 0.2

32

1 16

17

0.5 ± 0.1

0.3 ± 0.1 28.0 ± 0.3

0 ~ 15 10.16

1.778 0.15

0.15 ± 0.1

0.3Min.

7.8 ± 0.3 5.4 ± 0.2

1.8 ± 0.1 0.11 1 32

0.36 ± 0.1 16 17 13.6 ± 0.2

0.8