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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 6, JUNE 1996

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Optimization

of

Fully-Implanted

NPN’s for High-Frequency Operation

L. K. Nanver, E. J. G. Goudena, and H. W. van Zeijl

Abstract-With a very straightforward (low-cost) process flow as basis, fully-implanted washed-emitter-base (WEB) NPN’s have been optimized for operation in the 10-30 GHz range. Above 20 GHz the best overall performance is achieved by heavy doping of the epi. A low-stress silicon rich nitride layer is proven effective as surface isolation before contact window dip-etch.

1. INTRODUCTION

The performance of washed-emitter NPN’s can be significantly en- hanced by using the washed-emitter-base (WEB) processing scheme [1]-[3]. This flow preserves the low process complexity and high CMOS compatibility characteristic of fully-implanted NPN’s [4],

while at the same time making downscaling of the emitter below the micron possible, and boosting the frequency performance from the 5-10 GHz range to the 10-30 GHz range. In conventional washed- emitter processes the intrinsic base and link-base are formed in the same implantation step, while in the WEB flow each region is defined separately. A sidewall diode can then be formed which allows downscaling of the emitter without modification of the current gain, Early voltages or breakdown voltages. The major part of the intrinsic base is implanted after the emitter implantation directly

into the emitter contact window. This, along with the high degree of scalability, improves the reproducibility and parameter spread as well as providing a high degree of flexibility with respect to the preceding processing.

11. PROCESSING

Fig. 1 gives a schematic presentation of the WEB process. The 15-keV boron implantations for the extrinsic base and link-base are implanted through a 300-A thermal oxide. A 3000- 8, surface isolation layer is then deposited, whereafter all contact windows are plasma etched in one mask step. With a resist mask the emitters are implanted with 7.5 x arsenic at 40 keV, while the 20-keV boron intrinsic base is implanted without resist mask. All the dopants are activated by a single thermal anneal for 30 min at 950°C. After a wet dip-etch step to remove the native oxide, the windows are contacted by sputtering Al/l%Si. The metal pitch is 3 pm.

111. DEVICE CHARACTERISTICS

As shown in the SIMS doping profiles (1) and (3) of Fig. 2, the link-base and the emitter are both about 0.2-pm deep. The high surface doping of the link-base is decisive for the emitter- base breakdown voltage and the emitter sidewall capacitance, but other emitter sidewall characteristics such as current gain, Early voltage, emitter-collector breakdown voltage and cutoff frequency, are determined predominantly by the intrinsic base implantation. The Manuscript received February 23, 1995; revised February 6, 1996. The review of this brief was arranged by Editor T. Nakamura. This work was supported in part by Philips Semiconductors.

The authors are with Delft Institute of Microelectronics and Submicron Technology, DIMES IC Process Research Sector, Delft University of Tech-

nology, 2600 GB, Delft, The Netherlands.

Publisher Item Identifier S 001 8-9383(96)04032-4.

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Fig. 1. Schematical presentation of the WEB process flow.

emitters are found to be scalable with respect to the latter parameters

[ 11, independent of process variations in the link-base sheet resistance. Given the emitter-base structure, the cutoff frequency is determined by the collector configuration. With a 0.85-pm epi doped to 1016/cm3, an fr of 15 GHz and overall good device parameters are attained. The f r was increased by effectively increasing the collector doping either by heavily doping the epi doping or by reducing the epi thickness to bring the buried layer closer to the base. Some results are summarized in Table I. In all cases the emitter scalability and good low voltage characteristics are preserved, and the highest f~ x B V ~ E ~ product is obtained by increasing the epi doping.

IV. EMITTER-BASE STRUCTURE

In the WEB flow, the critical point in the formation of the intrinsic base is the amount of boron which is implanted through the emitter region. This is visualized in doping profile (1) of Fig. 2. Upon annealing the very high arsenic concentration gradient causes the arsenic to rapidly diffuse past the boron peak. The thermal diffusion of the remaining boron, less than 1% of the total implantation dose, is responsible for forming the actual base region.

If the intrinsic base is implanted before the emitter, channeling extends the depth of the implantation (doping profile (2) in Fig. 2(a)). With half the boron dose, the same base profile is formed as in (1). The same device characteristics can then be achieved, but relying on the channeling tail to form the base, increases the spread in current gain over the wafer from 100 & 10 to 100

*

25. This spread can be directly correlated to the nonuniformity of the implanter. No dependence on the plasma etching of the emitter windows has been detected. Such a dependence is commonly observed for cases where

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 6, JUNE 1996 1039 11 lo-- as-imolanted 21 10 20 10 h T

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10 19

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10 .- +- IS 0

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16 10 ? I 10 20 10

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i^ 19 'E 10

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I O 10 U C v 0 18 .-

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c 0 17 0 16 10 anneal: 950 C 30 min Fig. 2.

before the arsenic implant, and 3 ) 1.1 x 1014/cm2 boron implanted at 15 keV outside the arsenic region to form the link-base.

SlMS doping profiles of 1) 2.4 x 1014/cm2 boron implanted at 20 keV after the arsenic implant, 2) 1.2 x 10L4/cm2 boron implanted at 20 keV

TABLE I

DEVICE PARAMETERS OF WEB NPN's WITH DIFFERENT epi DOPING AND

THICKNESS. THE ON MASK EMITTER AREA IS 20 x 1 pm2.

the intrinsic base is implanted before the definition of the emitter window.

The fact that the emitter and intrinsic base are implanted at the end of the process gives a large degree of flexibility with respect to the preceding processing. Both thermal oxide and deposited dielectrics have been employed as surface isolation without altering the basic device characteristics. The most attractive surface isolation proved to be low-stress nitride. With nitride instead of oxide, the contact windows are not enlarged by the dip-etch step before metallization. By using a low-stress silicon rich nitride, SIN,, the attractive etch properties of Si3N.t are preserved, while the stress related problems are alleviated. Stress was evaluated by using a micro-machined test structure to directly determine the strain in the films [ 5 ] . For strains

from 2-3 x

lop3,

the frequency of e-c shorts increased rapidly with the strain. From 0.4 to 1.8 x lo-" defect-free characteristics were obtained [6].

Moreover, a very low llevel of nonideal base current was consis- tently achieved with LPCVD nitrides. Characteristic Gummel plots are displayed in Fig. 3. The observed base leakage is located at the surface where the link-base doping is high, and can be characterized as trap-assisted tunneling 161, [ 7 ] . The lower base leakage in the SiN,

samples is related to two properties of LPCVD nitrides: first, a high level of hydrogen is built into the SiN, films during deposition and can be partly released during alloying. Second, nitride forms a nearly impenetrable barrier to the diffusion of hydrogen. Thus, hydrogen for

1 o - ~ 1 o 6 lo-* 1 o ' O h v

-

d 400 300

2

200 IO0 ' 0 0.1 0.3 0.5 0.7 0.9 V B E (V) Fig. 3 .

isolation (dashed lines) with VBC := 0 .

GummeY plots of NPN's fabricated with SIN, (solid lines) and S i 0 2

the passivation of interface states is both supplied and contained at the interface by SIN, itself [SI. WO stable saturation of interface traps is achieved with the pure oxide isolation.

V. CONCLUSION

With the WEB NPN process, it has been possible to combine high performance with a low-cost process flow. The highest fT's

were achieved by heavily doping the epi layer. At f~ = 31 GHz, an f~ x B V m o = 96 GHzV was obtained, as compared to

f~

x B V C E ~ = 125 GHzV for the 15-GHz devices. A large degree of flexibility has been demonstrated in the process flow prior to the definition of the emitter and base, which both can be implanted after the surface isolation has been formed. Using a silicon-rich low-stress nitride instead of oxide is advantageous for the processing and reduces the nonideal base current component.

ACKNOWLEDGMENT

The authors wish to thank C. I. M. Beenakker for his continual support and encouragement, andl J. Slabbekoorn, A. van de Bogaard,

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1040 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 6, JUNE 1996

R. Mallee, P. J. French, S. Beckers, and W. Verveer for their [1] M. Norishima, H. Iwai, Y. Niitsu, and K. Maeguchi, “Impurity diffusion contributions to the experimental material. Thanks are also due to

J. Tauritz and M. d e Kok for the high-frequency measurements.

REFERENCES

[1] L. K. Nanver, E. J. G. Goudena, and H. W. van Zeijl, “Optimization of link-base in fully-implanted NPN’s,” Electronics Lett., vol. 29, pp.

1451-1452, 1993.

[2] T. H. Ning and R. D. Isaac, “Effect of emitter contact on current gain of bipolar devices,” IEEE Trans. Electron Devices, vol. ED-27, pp. 2051-2055, 1980.

131 I. R. C. Post, P. Ashhurn, and R. Wolstenholme, “Polysilicon emit- ters for bipolar transistors: A review and re-evaluation of theory and experiment,” IEEE Trans. Electron Devices, vol. 39, pp. 1717-1731, 1992.

behavior of bipolar transistor under low-tempirature furnace annealing and high-temperature RTA and its optimization for 0.5-pm Bi-CMOS process,” IEEE Trans. Electron Devices, vol. 39, pp. 33-40, 1992.

[ 5 ] B. P. van Drieenhuizen, J. F. L. Goosen, P. J. French, and R. F. Wolf-

fenbuttel, “Comparison of techniques for measuring both compressive and tensile stress in thin films,” Sensors and Actuators, vols. A37-38. pp. 756-765, 1993.

[6] L. K. Nanver, P. J. French, E. J. G. Goudena, and H. W. van Zeijl, “LOW stress nitride as surface isolation in bipolar transistors,” MateriuIs

Science and Technology, vol. 11, pp. 36-40, 1995.

[7] A. Chartre, G. Festes, G. Giroult-Matlakowski, and A. Nouailhat, “An investigation of nonideal base currents in advanced self-aligned ‘etched- polysilicon’ emitter bipolar transistors,” IEEE Trans. Electron Devices,

vol. 38. pp. 1354-1361, 1991.

[SI R. Hezel, K. Blumenstock, and R . Schomer, “Interface states and fixed charges in MNOS structures with APCVD and plasma silicon nitride,”

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