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Block Diagram

W dokumencie MC56F824X-3 (Stron 144-152)

Quad Timer (TMR)

6.4 Block Diagram

Each of the timer/counter groups within the quad-timer are shown in this figure.

COMP1

MUX OFLAG M

U X

OUTPUT

CAPTURE inputs

other cntrs

COMPARATOR

CMPLD1

COMP2 CMPLD2

IP_bus

CSCTRL CTRL PRESCALER

secondary primary

COMPARATOR

HOLD LOAD

COUNTER

Figure 6-1. Quad Timer Block Diagram

Memory Map and Registers

The address of a register is the sum of a base address and an address offset. The base address is defined at the chip level and the address offset is defined at the module level.

Make certain to check which quad timer is available on the chip being used, and which timer channels have external I/O.

Address

offset (hex) Register

name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 TMRA0_

COMP1

R COMPARISON_1

W

1 TMRA0_

COMP2

R COMPARISON_2

W

2 TMRA0_CAPT R

CAPTURE W

3 TMRA0_LOAD R

W LOAD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

6.5

Chapter 6 Quad Timer (TMR)

Address

offset (hex) Register

name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

4 TMRA0_HOLD R

W HOLD

5 TMRA0_CNTR R

COUNTER W

6 TMRA0_CTRL R

CM PCS SCS

ONCE LENGT

H DIR

COINIT

OUTMODE W

7 TMRA0_

SCTRL

R TCF

TCFIE TOF

TOFIE IEF

IEFIE IPS INPUT CAPTURE_ MODE MSTR EEOF VAL

0

OPS OEN

W FORCE

8 TMRA0_

CMPLD1

R COMPARATOR_LOAD_1

W

9 TMRA0_

CMPLD2

R COMPARATOR_LOAD_2

W

A TMRA0_

CSCTRL

R DBG_EN

FAULT ALT_ LOAD ROC TCI UP 0

TCF2EN TCF1EN TCF2 TCF1 CL2 CL1

W

B TMRA0_FILT R 0

FILT_CNT FILT_PER

W

F TMRA0_ENBL R 0

W ENBL

0 TMRA1_

COMP1

R COMPARISON_1

W

1 TMRA1_

COMP2

R COMPARISON_2

W

2 TMRA1_CAPT R

CAPTURE W

3 TMRA1_LOAD R

W LOAD

4 TMRA1_HOLD R

W HOLD

5 TMRA1_CNTR R

COUNTER W

6 TMRA1_CTRL R

CM PCS SCS

ONCE LENGT

H DIR

COINIT

OUTMODE W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address

offset (hex) Register

name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7 TMRA1_

SCTRL

R TCF

TCFIE TOF

TOFIE IEF

IEFIE IPS INPUT CAPTURE_ MODE MSTR EEOF VAL

0

OPS OEN

W FORC

E

8 TMRA1_

CMPLD1

R COMPARATOR_LOAD_1

W

9 TMRA1_

CMPLD2

R COMPARATOR_LOAD_2

W

A TMRA1_

CSCTRL

R DBG_EN

FAULT ALT_ LOAD ROC TCI UP 0

TCF2EN TCF1EN TCF2 TCF1 CL2 CL1

W

B TMRA1_FILT R 0

FILT_CNT FILT_PER

W

F T Reserved R 0

W RSVD

0 TMRA2_

COMP1

R COMPARISON_1

W

1 TMRA2_

COMP2

R COMPARISON_2

W

2 TMRA2_CAPT R

CAPTURE W

3 TMRA2_LOAD R

W LOAD

4 TMRA2_HOLD R

W HOLD

5 TMRA2_CNTR R

COUNTER W

6 TMRA2_CTRL R

CM PCS SCS

ONCE LENGT

H DIR

COINIT

OUTMODE W

7 TMRA2_

SCTRL

R TCF

TCFIE TOF

TOFIE IEF

IEFIE IPS INPUT CAPTURE_ MODE MSTR EEOF VAL

0

OPS OEN

W FORCE

8 TMRA2_

CMPLD1

R COMPARATOR_LOAD_1

W

9 TMRA2_

CMPLD2

R COMPARATOR_LOAD_2

W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address

offset (hex) Register

name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A TMRA2_

CSCTRL

R DBG_EN

FAULT ALT_ LOAD ROC TCI UP 0

TCF2EN TCF1EN TCF2 TCF1 CL2 CL1

W

B TMRA2_FILT R 0

FILT_CNT FILT_PER

W

F T Reserved R 0

W RSVD

0 TMRA3_

COMP1

R COMPARISON_1

W

1 TMRA3_

COMP2

R COMPARISON_2

W

2 TMRA3_CAPT R

CAPTURE W

3 TMRA3_LOAD R

W LOAD

4 TMRA3_HOLD R

W HOLD

5 TMRA3_CNTR R

COUNTER W

6 TMRA3_CTRL R

CM PCS SCS

ONCE LENGT

H DIR

COINIT

OUTMODE W

7 TMRA3_

SCTRL

R TCF

TCFIE TOF

TOFIE

IEF IEFIE IPS INPUT CAPTURE_ MODE MSTR EEOF VAL

0

OPS OEN

W FORCE

8 TMRA3_

CMPLD1

R COMPARATOR_LOAD_1

W

9 TMRA3_

CMPLD2

R COMPARATOR_LOAD_2

W

A TMRA3_

CSCTRL

R DBG_EN

FAULT ALT_ LOAD ROC TCI UP 0

TCF2EN TCF1EN TCF2 TCF1 CL2 CL1

W

B TMRA3_FILT R 0

FILT_CNT FILT_PER

W

F Reserved R 0

W RSVD

0 TMRB0_

COMP1

R COMPARISON_1

W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address

offset (hex) Register

name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 TMRB0_

COMP2

R COMPARISON_2

W

2 TMRB0_CAPT R

CAPTURE W

3 TMRB0_LOAD R

W LOAD

4 TMRB0_HOLD R

W HOLD

5 TMRB0_CNTR R

COUNTER W

6 TMRB0_CTRL R

CM PCS SCS

ONCE LENGT

H DIR

COINIT

OUTMODE W

7 TMRB0_

SCTRL

R TCF

TCFIE TOF

TOFIE IEF

IEFIE IPS INPUT CAPTURE_ MODE MSTR EEOF VAL

0

OPS OEN

W FORCE

8 TMRB0_

CMPLD1

R COMPARATOR_LOAD_1

W

9 TMRB0_

CMPLD2

R COMPARATOR_LOAD_2

W

A TMRB0_

CSCTRL

R DBG_EN

FAULT ALT_ LOAD ROC TCI UP 0

TCF2EN TCF1EN TCF2 TCF1 CL2 CL1

W

B TMRB0_FILT R 0

FILT_CNT FILT_PER

W

F TMRB0_ENBL R 0

W ENBL

0 TMRB1_

COMP1

R COMPARISON_1

W

1 TMRB1_

COMP2

R COMPARISON_2

W

2 TMRB1_CAPT R

CAPTURE W

3 TMRB1_LOAD R

W LOAD

4 TMRB1_HOLD R

W HOLD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address

offset (hex) Register

name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

5 TMRB1_CNTR R

COUNTER W

6 TMRB1_CTRL R

CM PCS SCS

ONCE LENGT

H DIR

COINIT

OUTMODE W

7 TMRB1_

SCTRL

R TCF

TCFIE TOF

TOFIE IEF

IEFIE IPS INPUT CAPTURE_ MODE MSTR EEOF VAL

0

OPS OEN

W FORCE

8 TMRB1_

CMPLD1

R COMPARATOR_LOAD_1

W

9 TMRB1_

CMPLD2

R COMPARATOR_LOAD_2

W

A TMRB1_

CSCTRL

R DBG_EN

FAULT ALT_ LOAD ROC TCI UP 0

TCF2EN TCF1EN TCF2 TCF1 CL2 CL1

W

B TMRB1_FILT R 0

FILT_CNT FILT_PER

W

F Reserved R 0

W RSVD

0 TMRB2_

COMP1

R COMPARISON_1

W

1 TMRB2_

COMP2

R COMPARISON_2

W

2 TMRB2_CAPT R

CAPTURE W

3 TMRB2_LOAD R

W LOAD

4 TMRB2_HOLD R

W HOLD

5 TMRB2_CNTR R

COUNTER W

6 TMRB2_CTRL R

CM PCS SCS

ONCE LENGT

H DIR

COINIT

OUTMODE W

7 TMRB2_

SCTRL

R TCF

TCFIE TOF

TOFIE IEF

IEFIE IPS INPUT CAPTURE_ MODE MSTR EEOF VAL

0

OPS OEN

W FORC

E

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address

offset (hex) Register

name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

8 TMRB2_

CMPLD1

R COMPARATOR_LOAD_1

W

9 TMRB2_

CMPLD2

R COMPARATOR_LOAD_2

W

A TMRB2_

CSCTRL

R DBG_EN

FAULT ALT_ LOAD ROC TCI UP 0

TCF2EN TCF1EN TCF2 TCF1 CL2 CL1

W

B TMRB2_FILT R 0

FILT_CNT FILT_PER

W

F Reserved R 0

W RSVD

0 TMRB3_

COMP1

R COMPARISON_1

W

1 TMRB3_

COMP2

R COMPARISON_2

W

2 TMRB3_CAPT R

CAPTURE W

3 TMRB3_LOAD R

W LOAD

4 TMRB3_HOLD R

W HOLD

5 TMRB3_CNTR R

COUNTER W

6 TMRB3_CTRL R

CM PCS SCS

ONCE LENGT

H DIR

COINIT

OUTMODE W

7 TMRB3_

SCTRL

R TCF

TCFIE TOF

TOFIE

IEF IEFIE IPS INPUT CAPTURE_ MODE MSTR EEOF VAL

0

OPS OEN

W FORCE

8 TMRB3_

CMPLD1

R COMPARATOR_LOAD_1

W

9 TMRB3_

CMPLD2

R COMPARATOR_LOAD_2

W

A TMRB3_

CSCTRL

R DBG_EN

FAULT ALT_ LOAD ROC TCI UP 0

TCF2EN TCF1EN TCF2 TCF1 CL2 CL1

W

B TMRB3_FILT R 0

FILT_CNT FILT_PER

W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address

offset (hex) Register

name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

F Reserved R 0

W RSVD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

6.5.1 Timer Channel Compare Register 1 (TMRx_COMP1)

Addresses: TMRA0_COMP1 – F000h base + 0h offset = F000h TMRA1_COMP1 – F010h base + 0h offset = F010h TMRA2_COMP1 – F020h base + 0h offset = F020h TMRA3_COMP1 – F030h base + 0h offset = F030h TMRB0_COMP1 – F040h base + 0h offset = F040h TMRB1_COMP1 – F050h base + 0h offset = F050h TMRB2_COMP1 – F060h base + 0h offset = F060h TMRB3_COMP1 – F070h base + 0h offset = F070h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read COMPARISON_1

Write

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

W dokumencie MC56F824X-3 (Stron 144-152)