Filtering and sampling settings should be changed only after
setting SE to 0 and FILTER_CNT to 0x0. These values have
the effect of resetting the filter to a known state.
3.6.1.1 Disabled Mode (1)
In disabled mode, the analog comparator is non-functional and consumes no power. The output of the analog comparator block (ACO) is zero in this mode. It is possible to further reduce power consumed by disabling the peripheral clock to the comparator logic. This is a function of the system integration module, or SIM.
3.6.1.2 Continuous Mode (2A and 2B)
-EN, PMODE INV FILTER_CNT
MMC[1:0]
OPE SE
1
WE
1 0
COS FILT_PER
0
COUT IER/F CFR/F PMC[1:0]
+
0
P0
P3 P1 P2
M1
M4 M2 M3
ACO
Polarity Select
Filter Block
Interrupt Control
IRQ
COUT
(To Other DSC Functions)
CMPO to Pad COUTA
CGMUX Window
Control
Peripheral Clock
FILT_PER Divided
Peripheral Clock
Windows/Sample
SE COS Internal Bus
Clock Prescaler
Figure 3-20. Comparator Operation in Continuous Mode
The analog comparator block is powered and active. ACO may be optionally inverted, but is not subject to external sampling or filtering. Both window control and filter blocks are completely bypassed. The SCR[COUT] bit is updated continuously. The path from comparator input pins to output pin is operating in combinational (unclocked) mode.
COUT and COUTA are identical.
3.6.1.3 Sampled, Non-Filtered Mode (3A and 3B)
-EN, PMODE INV FILTER_CNT
MMC[1:0]
OPE WE SE
COS FILT_PER
COUT IER/F CFR/F PMC[1:0]
+
WindowControl
Interrupt Control Filter
Block Polarity
Select
Peripheral Clock
FILT_PER Divided
Peripheral Clock Clock
Prescaler CMPO to
Pad
SE= 1 Internal Bus
CGMUX
COS Window/Sample
0 0x1 1
P0
P3 P1 P2
M1
M4 M2 M3
COUT
(To Other DSC Functions) IRQ
1
0
0
1
Figure 3-21. Sampled, Non-Filtered (3A): Sampling Point Externally Driven
In sampled, non-filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational (unclocked). Windowing control is completely bypassed. COUTA is sampled whenever a rising edge is detected on the filter block clock input.
The only difference in operation between Sampled, Non-Filtered (3A) and Sampled, Non-Filtered (3B) is in how the clock to the filter block is derived.
The comparator filter has no other function than sample/hold of the comparator output in
this mode.
-0 $1 1
EN, PMODE INV FILTER_CNT
MMC[1:0]
OPE WE SE
COS FILT_PER
COUT IER/F CFR/F PMC[1:0]
+
P0
P3 P1 P2
M1
M4 M2 M3
Peripheral Clock
FILT_PER Divided
Peripheral Clock
Window/Sample
SE=0 CGMUX
COS IRQ
COUT
(To Other DSC Functions)
CMPO to Pad Polarity
Select
Window Control
Filter Block
Interrupt Control
Clock Prescaler
1
0
0
1 Internal Bus
Figure 3-22. Sampled, Non-Filtered (# 3B): Sampling interval internally derived
3.6.1.4 Sampled, Filtered Mode (4A and 4B)
In sampled, filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational (unclocked). Windowing control is completely bypassed. COUTA is sampled whenever a rising edge is detected on the filter block clock input.
The only difference in operation between Sampled, Non-Filtered (3A) and Sampled,
Filtered (4A) is that FILTER_CNT is now greater than 1, which activates filter operation.
-EN, PMODE INV FILTER_CNT
MMC[1:0]
OPE WE SE
COS FILT_PER
COUT IER/F CFR/F PMC[1:0]
+
P0
P3 P1 P2
M1
M4 M2 M3
ACO
COS Clock
Prescaler
Window Control
Peripheral Clock FILT_PER
Window/Sample
COUT
(To Other DSC Functions)
CMPO to Pad Polarity
Select
Filter Block
Interrupt Control
IRQ
SE = 1
0 >0x1 1 Internal Bus
CGMUX
COUTA 1
0
0
1
Figure 3-23. Sampled, Filtered (4A): Sampling Point Externally Driven
-EN, PMODE INV FILTER_CNT SE
PMC[1:0] MMC[1:0]
OPE WE
COS FILT_PER
COUT
+
IER/F CFR/F Internal Bus
P0
P3 P1 P2
M1
M4 M2 M3
Peripheral Clock
FILT_PER
Clock
Prescaler Divided Peripheral Clock
Window/Sample
SE = 1
IRQ
COUT
(To Other DSC Functions)
CMPO to Pad ACO
COS CGMUX
COUTA 1
0
0
1 Polarity
Select
Window Control
Filter Block
Interrupt Control
0 >0x1 1
Figure 3-24. Sampled, Filtered (4B): Sampling Point Internally Derived
The only difference in operation between Sampled, Non-Filtered (3B) and Sampled, Filtered (4B) is that FILTER_CNT is now greater than 1, which activates filter operation.
3.6.1.5 Windowed Mode (5A and 5B)
The following image illustrates comparator operation in the windowed mode, ignoring latency of the analog comparator, polarity select and window control block. It also assumes that the polarity select is set to non-inverting. Note that the analog comparator output is passed to COUTA only when the WINDOW signal is high.
In actual operation, COUTA may lag the analog inputs by up to one peripheral clock
cycle plus the combinational path delay through the comparator and polarity select logic.
Window
P1–M1
ACO
COUTA
Figure 3-25. Windowed Mode Operation
+
-EN, PMODE INV FILTER_CNT IER/F CFR/F
PMC[1:0] MMC[1:0]
OPE WE SE
COS FILT_PER
COUT
P0
P3 P1 P2
M1
M4 M2 M3
Internal Bus
Polarity Select
Window Control
Filter Block
Interrupt Control
IRQ
COUT
(To Other DSC Functions)
CMPO to Pad Window/Sample
Peripheral Clock
SE = 0 Clock
Prescaler Divided Peripheral Clock FILT_PER
COUTA
CGMUX 1
0
0
1
0x1 0
Figure 3-26. Windowed Mode
When any windowed mode is active, COUTA is clocked by the peripheral clock
whenever WINDOW = 1. The last latched value is held when WINDOW = 0.
3.6.1.6 Windowed/Resampled Mode (6)
This example uses the same input stimulus shown in Figure 4-9, and adds resampling of COUTA to generate COUT. Samples are taken at the time points indicated by the arrows.
Again, prop delays and latency are ignored for clarity’s sake. This example was
generated solely to demonstrate operation of the comparator in windowing / resampled mode, and does not reflect any specific application. Depending upon the sampling rate and window placement, COUT may not see zero-crossing events detected by the analog comparator. Sampling period and/or window placement must be carefully considered for a given application.
Window
P1–M1
ACO
COUTA
COUT
Figure 3-27. Windowed / Resampled Mode Operation
This mode of operation results in an unfiltered string of comparator samples where the interval between the samples is determined by FILT_PER and the peripheral clock rate.
Configuration for this mode is virtually identical to that for the windowed/filtered mode
shown in the next section. The only difference is that the value of FILTER_CNT must be
exactly one.
3.6.1.7 Windowed/Filtered Mode (7)
Windowed/filtered mode is the most complex mode of operation for the comparator block because it uses both windowing and filtering features. It also has the highest
latency of any mode. This can be approximated: up to 1 peripheral clock synchronization in the window function + ((FILTER_CNT X FILT_PER) + 1) X peripheral clock for the filter function.
When any windowed mode is active, COUTA is clocked by the peripheral clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0.
+
-EN, PMODE INV FILTER_CNT
MMC[1:0]
OPE WE SE
COS FILT_PER
COUT IER/F CFR/F PMC[1:0]
-+
P0
P3 P1 P2
M1
M4 M2 M3
Polarity Select
Window Control
Filter Block
Interrupt Control ACO
COS COUT
(To Other DSC Functions) Internal Bus
IRQ
Peripheral Clock
FILT_PER Divided
Peripheral Clock
Window/Sample
CMPO to Pad COUTA
CGMUX SE = 0 Clock
Prescaler
1
0
0
1
>0x1 0 1
Figure 3-28. Windowed/Filtered Mode
3.6.2 Power Modes
The following table summarizes the terms that apply for each power mode.
Table 3-22. Freescale Power Modes
Power Mode Comments
Run Normal operating mode
Table continues on the next page...
Table 3-22. Freescale Power Modes (continued)
Power Mode Comments
Wait Processor halted, peripherals continue to run.
Stop Processor and peripheral clocks halted. Regulator is fully engaged.
3.6.2.1 Wait Mode Operation
During wait mode the HSCMP, if enabled, continues to operate normally. Also, if enabled, the interrupt can wake the DSC core.
3.6.2.2 Stop Mode Operation
The DSC core is brought out of stop when a compare event occurs and corresponding interrupt is enabled. Similarly, if the CR1[OPE] bit is set to 1, the comparator output operates as in the normal operating mode and the comparator output is placed onto the external pin.
If stop is exited with a reset, all comparator registers are put into their reset state.
Windowed, sampled, and filtered modes of operation continue to operate in stop mode if the clock to the peripheral is enabled for stop. Edge detection for compare events also requires a peripheral clock. None of these features function correctly unless the clock to the HSCMP is enabled for stop (via the SIM stop disable registers).
3.6.2.3 Debug Mode Operation
When the DSC is in debug mode, the HSCMP continues to operate normally.
3.6.3 Hysteresis
The following figure illustrates implementation of an external hysteresis resistor bridge between the asynchronous comparator output and the positive (+) input of the
comparator. Because positive feedback is required, INV must be set to 0 when the
hysteresis resistor bridge is added to the positive (+) input of the comparator. INV must
be set to 1 when the hysteresis resistor bridge is added to the negative (–) input of the
comparator.
The option of adding an external resistor bridge for the purpose of adding hysteresis to the comparator and the amount of hysteresis depends on the user’s individual
requirements. Hysteresis can be important in some system designs. In the absence of hysteresis, the continuous comparison of nearly identical analog inputs may add noise and waste power by generating high-frequency oscillations at CMPO.
If external hysteresis is added to the comparator, the bridge must be designed to consider other issues than how much hysteresis is needed. The resistor values must be sufficiently high so that they do not cause the drive strength of the digital output driver in the CMPO IO circuitry to be exceeded. Also, if any digital function other than CMPO must operate on the CMPO pad in the presence of such a bridge, the resistor values must be
sufficiently high so that the IO circuitry can function appropriately in its digital role.
-+
I/O Circuitry
INV = 0 Px
My CMPO
COS EXOR
Input 1
Input 2
COUTA