DAC_MAXVAL [FORMAT=1] field descriptions

Field Description

15–4

MAXVAL Maximum value (left justified)

When the DAC is in automatic mode (CTRL[AUTO] = 1), the maximum value contained in this register will act as the upper range limit during automatic waveform generation. This register is not used during normal mode operation, but can still be written to and read from. Please refer to the chip data sheet for limitations on the high end voltage output of the DAC.

NOTE: If DAC input data is greater than MAXVAL, output will be limited to MAXVAL during automatic waveform generation.

3–0 Reserved

This read-only bitfield is reserved and always has the value zero.

5.3 Functional Description

5.3.1 Conversion modes

This DAC supports two conversion modes: asynchronous conversion and synchronous conversion.

5.3.1.1 Asynchronous conversion mode

Data can be immediately presented to the DAC and converted to an analog output when it

is written to the DAC buffered data register.

5.3.1.2 Synchronous conversion mode

Data in the DAC buffered data register is controlled by the SYNC_IN signal when the buffered data is presented to the input of the DAC. The update occurs on the rising edge of the SYNC_IN signal. The SYNC_IN signal can come from a timer, comparators, pins, or other sources. The CPU needs to update the buffered data register prior to the next SYNC_IN rising edge. Otherwise, the old buffered data is reused. Note: The SYNC_IN single must be high for at least one IPBus clock cycle and must be low for at least one IPBus clock cycle.

5.3.2 Operation Modes

The DAC operates in either Normal or Automatic mode. In Normal mode, it generates an analog representation of digital words. In Automatic mode, it generates sawtooth,

triangle, and square waveforms without CPU intervention.

5.3.2.1 Normal Mode

The DAC receives data words through a memory-mapped register on the IPBus (DATA).

A digital word is applied to the DAC inputs based on CTRL[SYNC_EN]. In the worst case with no DAC output load, approximately 240 ns settling time is needed.

5.3.2.2 Automatic Mode

In Automatic mode, the DAC generates sawtooth, triangle, and square wave waveforms without CPU intervention. The update rate, incremental step size, and minimum and maximum values are programmable.

The value in the DATA register is used as a starting-point for the following process:

1. The SYNC_IN input indicates that it is time to update the data presented to the DAC.

2. The STEP value is added to/subtracted from the current DATA value and DATA is updated.

3. If CTRL[UP] is set, then STEP is added to DATA each update until MAXVAL is reached.

4. The generator starts subtracting STEP from DATA if CTRL[DOWN] is set (down counting enabled) or reloading MINVAL if CTRL[DOWN] is clear (no down counting).

5. When DATA reaches MINVAL while counting down, the generator starts counting

up if CTRL[UP] is set or reloads MAXVAL if CTRL[UP] is clear (up counting

disabled).

The initial count direction depends on which bit (CTRL[UP] or CTRL[DOWN]) is set last.

The following figures show examples of automatically-generated waveforms. The waveforms shown are ideal. Actual waveforms are limited by the slew rate of the DAC output.

STEP VDD

MAXVAL

MINVAL

VSS

SYNC_IN

Figure 5-11. Sawtooth Waveform Example with CTRL[UP]=1 and CTRL[DOWN]=0

VDD

MAXVAL

STEP

MINVAL

VSS

SYNC_IN

Figure 5-12. Triangle Waveform Example with CTRL[UP]=1 and CTRL[DOWN]=1

VDD

MAXVAL

MINVAL

VSS

SYNC_IN

Figure 5-13. Square Waveform Example with CTRL[UP]=1 and CTRL[DOWN]=1

These examples show that the waveform period is a function of the difference between MAXVAL and MINVAL, the STEP size, and the update rate as shown here:

Increasing STEP decreases the resolution of the output steps. Increasing the update rate decreases the waveform period. Varying MINVAL and MAXVAL changes the DC offset and the amplitude of the waveform.

5.3.3 DAC settling time

Settling time is the interval, within a specified percentage error band, between the time data is presented to the DAC input to update (change) and the time its analog output value reaches its final value. Settling time is affected by circuit propagation delay and the slew rate of the DAC output capability, plus the real load on DAC output.

Approximately 240 ns settling time, which is caused by the DAC conversion glitch, is

needed in the worst case situations when DAC output is internally fed to other modules,

such as comparator inputs. If DAC output is to a package pin, the additional settling time

is affected by the slew rate of an output amplifier and the load on the pin. The maximum

settling time will not exceed 2 microseconds with a maximum output load (3 kohm || 400

pf) when the output swings from minimum output to maximum output or vice-versa.

5.3.4 Waveform Programming Example

To create a waveform that goes down from 3.0 V to 1.5 V in 1 millisecond, first calculate MAXVAL and MINVAL. Based on each DAC LSB representing 0.806 mV (assuming the DAC reference is 3.3 V), we find that MAXVAL is 0xE8A and MINVAL is 0x745.

These numbers represent a difference of 1861 LSBs to be accomplished in 1 millisecond, so we can safely update the DAC 500 times because the DAC has a maximum

2-microsecond settling time. Programming calculations are as follows:

• To go from MAXVAL to MINVAL in 500 steps, STEP must be 0x004 after rounding the result of 1861/500.

• To go from MAXVAL to MINVAL with a STEP size of 0x004 requires 465.25 steps.

• To keep the waveform period of 1 millisecond using 465.25 updates requires an update period of 465.25 KHz.

• If the system clock operates at 60 MHz, program a timer module to pulse the SYNC_IN input every 60000000/465250 = 129 counts.

When the timer module is programmed along with the MAXVAL, MINVAL, and STEP registers, the DATA register is written with a value equal to MAXVAL as a starting point because the DAC is only down counting. When writing to the DATA, STEP, MAXVAL, and MINVAL registers, ensure that FORMAT has the desired value and that the data values are properly justified to match FORMAT. The SYNC_EN, DOWN, and AUTO bits of the CTRL register should be set. The CTRL[UP] and CTRL[PDN] bits are cleared. To suppress glitches on the output, set CTRL[FILT_CNT] and

CTRL[FILT_EN]. The desired waveform starts within 12 microseconds from the clearing

of CTRL[PDN] and continues until CTRL[PDN] is set or the timer is stopped.