TMRx_ENBL field descriptions
Channel 1 works in cascaded count mode receiving its counting instructions from channel 0. When an input capture event occurs, channel 1 is programmed to reset its counter
6.6.2.6 Quadrature-Count Mode with Index Input
As an extension to the quadrature count mode discussed in the previous paragraph, some rotary shafts have a HOME or INDEX indicator. This would be a third input to the timer that is used to reset the timer's counter.
In this example, channel 0 is used to decode the quadrature inputs, but it doesn't actually count. Because its upper and lower limits are both set to 0, its output is cascaded count up and count down signals each time the quadrature inputs indicate a change in count.
Channel 1 works in cascaded count mode receiving its counting instructions from channel
Example: 6.6.2.7.1 Signed Count Mode Example
// (See Processor Expert PulseAccumulator bean.) // This example uses TMRA0 for signed mode counting.
//// Timer input 2 is used as the primary count source.
// Timer input 1 is used to determine the count direction.
//void Pulse_Init(void) {
/* TMRA0_CTRL: CM=0,PCS=2,SCS=1,ONCE=0,LENGTH=0,DIR=0,Co_INIT=0,OM=0 */
setReg(TMRA0_CTRL,0x0480); /* Set up mode */
/* TMRA0_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=1,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
setReg(TMRA0_SCTRL,0x1000);
setReg(TMRA0_CNTR,0x00); /* Reset counter register */
setReg(TMRA0_LOAD,0x00); /* Reset load register */
setRegBitGroup(TMRA0_CTRL,CM,0x05); /* Run counter */
}
>
6.6.2.8 Triggered-Count Mode 1
If CSCTRL[TCI] is clear and CTRL[CM] is set to '110', the counter will begin counting the primary clock source after a positive transition (negative edge if SCTRL[IPS]=1) of the secondary input occurs. The counting will continue until a compare event occurs or another positive input transition is detected. If a second input transition occurs before a terminal count is reached, counting will stop and SCTRL[TCF] (timer compare flag) will be set. Subsequent secondary input transitions will continue to restart and stop the
counting until a compare event occurs.
COMP1 = 18 timer_out
Secondary Count Primary
18
12 13 14 15 16 17
Figure 6-120. Triggered Count Mode 1 (CTRL[LENGTH]=0)
Example: 6.6.2.8.1 Triggered Count Mode 1 Example
// (See Processor Expert PulseAccumulator bean.) // This example uses TMRA1 for triggered mode counting.
//// Timer input 3 is used as the primary count source.
// Timer input 2 is used for the trigger input.
//void Pulse_Init(void) {
/* TMRA1_CTRL: CM=0,PCS=3,SCS=2,ONCE=0,LENGTH=0,DIR=0,Co_INIT=0,OM=0 */
setReg(TMRA1_CTRL,0x0700); /* Set up mode */
/* TMRA1_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=1,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
setReg(TMRA1_SCTRL,0x1000);
setReg(TMRA1_CNTR,0x00); /* Reset counter register */
setReg(TMRA1_LOAD,0x00); /* Reset load register */
setReg(TMRA1_COMP1,0x0012); /* Set up compare 1 register */
/* TMRA1_CSCTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0, TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
setReg(TMRA1_CSCTRL,0x00);
setRegBitGroup(TMRA1_CTRL,CM,0x06); /* Run counter */
}
>
6.6.2.9 Triggered-Count Mode 2
If CSCTRL[TCI] is set and CTRL[CM] is set to '110', the counter will begin counting the primary clock source after a positive transition (negative edge if SCTRL[IPS]=1) of the secondary input occurs. The counting will continue until a compare event occurs or another positive input transition is detected. If a second input transition occurs before a terminal count was reached, the counter will reload and continue counting. When
CSCTRL[TCI] is set, the OFLAG output mode, CTRL[OUTMODE], should probably be set to '101' (cleared on init, set on compare) to ensure the output will be in a known state after the second input transition and subsequent reload takes place.
Secondary
Count 0 0 0 0 1 2 3 4 5 6 7 8 0 1 2 3 0 1 2 3 4 5 6 7
Figure 6-121. Triggered Count Mode 2 (CTRL[LENGTH]=0)
Example: 6.6.2.9.1 Triggered Count Mode 2Example
// (See Processor Expert PulseAccumulator bean.) // This example uses TMRA1 for triggered mode counting.
//// Timer input 3 is used as the primary count source.
// Timer input 2 is used for the trigger input.
//void Pulse_Init(void) {
/* TMRA1_CTRL: CM=0,PCS=3,SCS=2,ONCE=0,LENGTH=0,DIR=0,Co_INIT=0,OM=0 */
setReg(TMRA1_CTRL,0x0700); /* Set up mode */
/* TMRA1_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=1,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
setReg(TMRA1_SCTRL,0x1000);
setReg(TMRA1_CNTR,0x00); /* Reset counter register */
setReg(TMRA1_LOAD,0x00); /* Reset load register */
setReg(TMRA1_COMP1,0x0012); /* Set up compare 1 register */
/* TMRA1_CSCTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0, TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
setReg(TMRA1_CSCTRL,0x00);
setRegBitGroup(TMRA1_CTRL,CM,0x06); /* Run counter */
}
>
6.6.2.10 One-Shot Mode
If CTRL[CM] is set to '110', and the counter is set to reinitialize at a compare event (CTRL[LENGTH]=1),and CTRL[OUTMODE] is set to '101' (cleared on init, set on compare), the counter works in a one-shot mode. An external event causes the counter to count, and when the terminal count is reached, the output is asserted. This delayed output can be used to provide timing delays.
LOAD = 0, COMP1 = 4 timer_out
Secondary Count Primary
4
2 3 2 3
1 1
0 0
Figure 6-122. One-Shot Mode (CTRL[LENGTH]=1)
Example: 6.6.2.10.1 One-Shot Mode Example
// (See Processor Expert PulseAccumulator bean.) // This example uses TMRA1 for one-shot mode counting.
//// Timer input 3 is used as the primary count source.
// Timer input 2 is used for the trigger input.
//void Pulse_Init(void) {
/* TMRA1_CTRL: CM=0,PCS=3,SCS=2,ONCE=0,LENGTH=0,DIR=0,Co_INIT=0,OM=5 */
setReg(TMRA1_CTRL,0x0725); /* Set up mode */
/* TMRA1_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=1,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
setReg(TMRA1_SCTRL,0x1000);
setReg(TMRA1_CNTR,0x00); /* Reset counter register */
setReg(TMRA1_LOAD,0x00); /* Reset load register */
setReg(TMRA1_COMP1,0x0004); /* Set up compare 1 register */
/* TMRA1_CSCTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0, TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
setReg(TMRA1_CSCTRL,0x00);
setRegBitGroup(TMRA1_CTRL,CM,0x06); /* Run counter */
}
>
6.6.2.11 Cascade-Count Mode
If CTRL[CM] is set to '111', the counter's input is connected to the output of another selected counter. The counter will count up and down as compare events occur in the selected source counter. This cascade or daisy-chained mode enables multiple counters to be cascaded to yield longer counter lengths. When operating in cascade mode, a special high-speed signal path is used between modules rather than the OFLAG output signal. If the selected source counter is counting up and it experiences a compare event, the counter will be incremented. If the selected source counter is counting down and it experiences a compare event, the counter will be decremented.
Up to four counters may be cascaded to create a 64-bit wide synchronous counter. Check the data sheet to see if there are any frequency limits for cascaded counting mode.
Whenever any counter is read within a counter module, all of the counters' values within the module are captured in their respective hold registers. This action supports the
reading of a cascaded counter chain. First read any counter of a cascaded counter chain,
then read the hold registers of the other counters in the chain. The cascaded counter mode
is synchronous.
Note
It is possible to connect counters together by using the other (non-cascade) counter modes and selecting the outputs of other counters as a clock source. In this case, the counters are
operating in a ripple mode, where higher order counters will transition a clock later than a purely synchronous design.
Example: 6.6.2.11.1 Generate Periodic Interrupt Cascading Two Counters
// (See Processor Expert TimerInt bean.)
// This example generates an interrupt every 30 seconds, // assuming the chip is operating at 60 MHz.
//
// To do this, counter 2 is used to count 60,000 IP_bus clocks, which means it // will compare and reload every 0.001 seconds.
// Counter 3 is cascaded and used to count the 0.001 second ticks and // generate the desired interrupt interval.
//void TimerInt_Init(void) {
// Set counter 2 to count IP_bus clocks
/* TMRA2_CTRL: CM=0,PCS=8,SCS=0,ONCE=0,LENGTH=1,DIR=0,Co_INIT=0,OM=0 */
setReg(TMRA2_CTRL,0x1020); /* Stop all functions of the timer */
// Set counter 3 as cascaded and to count counter 2 outputs
/* TMRA3_CTRL: CM=7,PCS=6,SCS=0,ONCE=0,LENGTH=1,DIR=0,Co_INIT=0,OM=0 */
setReg(TMRA3_CTRL,0xEC20); /* Set up cascade counter mode */
/* TMRA3_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
setReg(TMRA3_SCTRL,0x00);
/* TMRA2_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
setReg(TMRA2_SCTRL,0x00);
setReg(TMRA3_CNTR,0x00); /* Reset counter register */
setReg(TMRA2_CNTR,0x00);
setReg(TMRA3_LOAD,0x00); /* Reset load register */
setReg(TMRA2_LOAD,0x00);
setReg(TMRA3_COMP1, 30000); /* milliseconds in 30 seconds */
setReg(TMRA3_CMPLD1,30000);
setReg(TMRA2_COMP1, 60000); // Set to cycle every milisecond setReg(TMRA2_CMPLD1,60000);
/* TMRA3_CSCTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0, TCF2EN=0,TCF1EN=1,TCF2=0,TCF1=0,CL2=0,CL1=1 */
setReg(TMRA3_CSCTRL,0x41); /* Enable compare 1 interrupt and */
/* compare 1 preload */
/* TMRA2_CSCTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0, TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=1 */
setReg(TMRA2_CSCTRL,0x01); /* Enable Compare 1 preload */
setRegBitGroup(TMRA2_CTRL,CM,0x01); /* Run counter */
}