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Abstract—Laboratory of the Department of Electronics AGH has among others, didactic stand with PC603E processor. It consists of cards using VME standard, plus embedded software (editor, assembler, monitor). This article describes hardware solutions of CPU card. The main finite state machine, its flow chart and selected timing are presented. The dedicated diagnostic system works with the PC603E card. It uses the JTAG port implemented in the PC603E. Diagram of the diagnostic circuit and the significant problems, associated with versions of JTAG port implementation are demonstrated.
Index Terms—VME standard, JTAG port, Power PC 603E
I. INTRODUCTION
RCHITECTURE of Power PC is used in host processors and telecommunication applications. In this case, on a chip different versions of QUICC (Quad Integrated Communication Controller) co-processor are installed. Processors, just mentioned, are produced by Freescale Semiconductor. These series are: MPC 603E, MPC 7XX, MPC 86X for host processors and MPC 860, ‘8260, ‘83XX, ‘85XX and MPC 8XX for telecommunication. They are used in CISCO net equipment.
Inside processor, different versions of core are installed: MPC8XXX, e300, e500 and e600. The main difference between them is set of Special Purpose Registers (SPR) for memory management, cache memory and performance monitoring. Registers set for user level are in fact very similar. Floating Point Unit (FPU) for core e500 has already 64 bits format for General Purpose Registers (GPR).
Communication between processor and internal peripheral is standard. Processor simply uses location in internal data memory.
Even through the differences are significant, all Power PC processors have very similar bus structure at their disposal. In this article hardware problems of PC 603E processor will be
Manuscript received November 7, 2011.
B. J. Wiśniewski, Department of Electronics, AGH University of Science and Technology , al. Mickiewicza 30, 30-059 Krakow, Poland (corresponding author phone: 0048 609 192 139; fax: 0048 12 633 23 98 ; e-mail: bwisniew@agh.edu.pl).
B. E. Szecówka-Wiśniewska, Department of Electronics, AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Krakow, Poland (e-mail: bawisnie@agh.edu.pl).
presented. First issue is adjustment to VME bus. Second issue is development of diagnostic circuit, which uses JTAG port.
II. COOPERATIONOFMICROPROCESSORPC603E WITHVMEBUS
Power PC processors execute bus cycles in asynchronous mode. They are adapted for working in normally unready systems (!TA signal - ! means negation). Therefore, they have exception of hardware error (!TEA signal) at their disposal. Faulty cycle can be repeated (!DRTRY signal). The set of signals used within bus cycle is presented in Fig. 1.
TS
DB (Data Bus) A0 - A31 (Address Bus) AP0 - 3 (Address Parity)
Address Atributes
DP0 - 7 (Data Parity) APE (Address Parity Enable)
ARTRY AACK DBDIS DRTRY TEA TA DBE (Transfer Start) Address Bus Address Termination Data Transfer Data Termination (Address Acknowledge) PC 603E
(Data Bus Disable) (Data Bus Enable) (Transfer Acknowledge)
(Data Retry) (Transfer Error Acknowledge)
(Address Retry)
Fig. 1. Chosen signals of PC 603E bus.
Bus cycles can be single or burst. Transfer of the whole line to or from cache memory occurs while using burst cycle. Logic of burst cycles is initiated after cache memory activation. The bus cycle can be divided into two phases: transfer and address. These phases can be executed independently and thus pipelining is possible. In this case line !AACK is used – independently from acknowledging the address.
Standard VME has different set of signals both status and controlling [1]. Their functions do not respond straight to signals of PC603E processor.
PC603E processor “does not normally use” the bus. Bus request (!BR signal – Bus Request) is given generally in the case of a miss, while contacting with cache memory. After the bus has been received (!BG signal – Bus Grant) processor informs about its engagement using !ABB (Address Bus Busy)
Card with the PC 603E Processor - Cooperation
with VME Bus and JTAG Port Interface
Bogusław J. Wiśniewski, Barbara E. Szecówka - Wiśniewska
A
> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2 line. It’s bi-directional line. Before processor definitely
overtakes the bus, it checks its state. Low active level informs, that another card–type “Master” is still using the bus (Fig. 2).
Finite State Machine Termi-nation Logic BR i BG i BB BCLR SYSRESET Initial Logic Clock Logic PC 603E AM5 - 0: A Q B Q C Q D Q CEP CET PE BR BG ABB DBB TS TA TEA TBST TT4-0 TC1,0 :
ARTRY DBWO DRTRY AACK
JTAG Intenal frequency multiplication PLLCFG0-3 SYSCLK : Gene-rator RUN + STOP STEP O O O O O O O O
Note: Open collector gates
O O R C BERR R/W DTACK DS0 DS1 AS V M E System cards SYSRESET HRESET 'HC161 1 T=60 us Manual Reset VCC VCC 1 1 A r b i t e r CLR
Fig. 2. Main finite state machine of CPU card – simplified circuit
During active level of Reset signals, processor tests the state of configuration lines. It was established on the card:
!DRTRY = 0 (work without repeating bus cycles), !TLBISYNC = 0 (data bus reduced to 32 bits).
Signal conversion between processor and VME bus is realized by finite-state machine. Its flow chart is presented in Fig. 3.
BG
1 0
BR
1 0
SYSRESET
BR ;BG; BB; AS; DS0,1; TA; TEA 0 0 0 0 0 0 0
1 0 0 0 0 0 0 i AS 1 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 TS 1 0 ABB 1 0 DBB 1 0 0 1 1 1 1 0 0 BERR 1 0 DTACK 1 0 0 1 1 1 1 1 0 TBST 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 BR 1 0 Q 1 0
Output signals (positive logic)
states
D
0 1 1 0 0 0 0
Fig. 3. Main finite state machine of CPU card – flow chart
Finite-state machine is synchronized by falling clock side, opposite to the processor. Fig. 4 shows timing for single and burst cycles of processor and VME bus.
ABB DTACK BERR NORMAL CYCLE IN / OUT PC 603E SYSCLK ARBITER BR i BR i BG BB BG TS AS DBB DS0,1 TA TBST QD TEA DTACK CARD LOGIC NORMAL CYCLE BURST CYCLE BURST CYCLE WAIT STATES INSTEAD TA N O R M A L B U S E R R O R
Fig. 4. Main finite state machine of CPU card – timing
PC6xx processors have full static logic at their disposal. That is why on the card, step-by step work of signal clock was anticipated. This mechanism is used for test and observational purposes during lab classes.
PC6xx processors meet the requirements of MEI protocol. Coherence of cache memory is assured, despite the work in write-back mode. Inactive processor snoops into the state of the address together with the line of its synchronization (!TS). If it finds the connection – data read type then processor checks its own cache memory. If included data were not copied to main memory than emergency protocol is initiated. Using !ARTRY signal, processor informs arbiter about it. Arbiter hands over the bus to processor, for realization of actualization cycle. After it is finished, the bus is returned and an active processor repeats the cycle (data is already valid). Because of single work of a card, this mechanism was not installed.
III. DIAGNOSTICDEVICEUSINGJTAGPORT In PC6xx processor from the very beginning testing port JTAG is installed together with the standard order set: BYPASS, SAMPLE/PRELOAD and EXTEST [2]. In the later versions also CLAMP(*) and HIGHZ functions have been added. (*Output lines are set in the safe state according to Boundary Scan Register (BSR) bits. Command includes itself also BYPASS function.)
The length of BSR was 189 bits at the beginning. However, in the newer versions it is 190 bits. In the first versions we deal with the incompatibility with IEEE 1149.1 standards. It is concerned with the operation of HRESET and CKSTP_IN lines. Number of processor version is saved in Processor Version Register (PVR). It is, however, not available through JTAG port (command IDCODE does not occur). Version of JTAG port can be checked only through tests. We check, how many clock periods (189/190) is necessary to transmit data
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can be chosen and so the organization of BSR register. External diagnostic circuit of JTAG port was built as a typical application of 80C52 microcontroller (Fig. 5).
Fig. 5. Scheme of JTAG port interface
It consists of hexadecimal keyboard plus function keys, 4-line LCD screen and additional RAM memory (for archive purposes). JTAG standard signals are supported by P1 port. The application has the possibility to contact master computer through port type SCI. The work of diagnostic circuit was made to resemble the solutions used in laboratory for other processors. The novelty is the necessity to choose processor version “manually” on the basis of dedicated built-in test.
IV. CONCLUSIONS
Card with PC 603E processor and JTAG port console was made and then tested (Fig. 6).
Result of practical tests confirmed rightness of initial assumptions. The card works correctly, together with the existing equipment of VME bus [3]. It concerns especially, multi – purpose VME console for control and observation. Thanks to it, it is possible step – by – step work and address trap installation.
After installing existing card (RAM memory, EPROM, screen and keyboard), the whole laboratory stand was created. Its additional part is equipped in testing JTAG port. For this stand, dedicated software (monitor – debugger, editor, assembler - disassembler) was prepared. Gain experience make it easier to construct two following cards with communication processors (MPC 860, MPC 8260).
They include PC 603E core. It will make possible to use important part of already prepared software.
Fig. 6. View of the card with JTAG interface
REFERENCES
[1] VME Standard, http://www.vita.com
[2] JTAG boundary – scan, IEEE 1149.1
[3] B. J. Wiśniewski, „Środki uruchomieniowe w laboratorium
dydaktycznym Techniki Mikroprocesorowej”, Elektronika :
konstrukcje, technologie, zastosowania, vol. 50, no.10, pp. 42-45, Oct.
2009. CPU (PC 603E) LCD Panel (4 x 16) WR RD EPROM TDI TDO TMS TCK TRST 30 5V6 P1.0 P1.1 P1.3 P1.2 P1.4 P0 P2 Reset P1.5 P1.6 R/S E D0 D7 R/W '574 AD0 AD3 '574 . . . Q Q DQ DQ 0 7 0 7 RAM 27512 6164 1 2 8 Q Q Q AD0 AD7 A0 A7 A8 A15 A0 A7 A8 A15 CS OE Keyboard '245 A B D I R A8 A15 INTR0 INTR1 T0 T1 10 u 8k2 + MAX 232 plus capa-citors TxD RxD RS 232 '573 CE OE ALE PSEN A14 A15 80C52 AD0 AD7 CLK G OE L
