Exception Syndrome Register (ESR)

The ESR, shown in Figure 2-18, provides a syndrome to distinguish exceptions that can generate the same interrupt type. The e200z3 adds implementation-specific bits to this register.

Table 2-12. IVOR Assignments

IVOR Number SPR Interrupt Type

IVOR0 400 Critical input IVOR1 401 Machine check IVOR2 402 Data storage IVOR3 403 Instruction storage IVOR4 404 External input IVOR5 405 Alignment IVOR6 406 Program

IVOR7 407 Floating-point unavailable IVOR8 408 System call

IVOR9 409 Auxiliary processor unavailable. (Defined by the EIS but not supported in the e200z3.) IVOR10 410 Decrementer

IVOR11 411 Fixed-interval timer interrupt IVOR12 412 Watchdog timer interrupt IVOR13 413 Data TLB error

IVOR14 414 Instruction TLB error

IVOR15 415 Debug

IVOR16–IVOR31 — Reserved for future architectural use IVOR32 528 SPE APU unavailable (EIS–defined)

IVOR33 529 SPE floating-point data exception (EIS–defined) IVOR34 530 SPE floating-point round exception (EIS–defined) IVOR35–IVOR63 — Allocated for implementation-dependent use

Figure 2-18. Exception Syndrome Register (ESR)

NOTE

ESR information is incomplete, so system software may need to identify the type of instruction that caused the interrupt and examine the TLB entry and the ESR to identify the exception or exceptions fully. For example, a data storage interrupt can be caused by both a protection violation exception and a byte-ordering exception. System software must check beyond ESR[BO], such as the state of MSR[PR] in SRR1 and the TLB entry page protection bits, to determine whether a protection violation also occurred.

The ESR fields are described in Table 2-13.

32 35 36 37 38 39 40 41 42 43 44 45 46 47 48 55 56 57 58 5 61 62 63

Field — PIL PPR PTR FP ST — DLK ILK AP PUO BO PIE — SPE — VLEMI — MIF XTE

Reset All zeros

R/W R/W

SPR SPR 62

Table 2-13. ESR Field Descriptions

Bits Name Description Associated Interrupt Type

32–35 — Reserved, should be cleared. —

36 PIL Illegal instruction exception Program

37 PPR Privileged instruction exception Program

38 PTR Trap exception Program

39 FP Floating-point operation Alignment, data storage, data TLB, program

40 ST Store operation Alignment, data storage, data TLB

41 — Reserved, should be cleared. —

42 DLK Data cache locking¹ Data storage

43 ILK Instruction cache locking Data storage`

44 AP Auxiliary processor operation. (unused in the e200z3) Alignment, data storage, data TLB, program 45 PUO Unimplemented operation exception Program

46 BO Byte ordering exception Data storage

47 PIE Program imprecise exception. Unused in the e200z3 (Reserved, should be cleared.)

—

48–55 — Reserved, should be cleared. —

56 SPE SPE APU operation SPE unavailable, SPE floating-point data exception, SPE floating-point round exception, alignment, data storage, data TLB

57 — Reserved, should be cleared. —

2.9.1 VLE Mode Instruction Syndrome

ESR[VLEMI] indicates when an interrupt is caused by a VLE instruction. This syndrome bit is set on an exception associated with execution or attempted execution of a VLE instruction. This bit is updated for the interrupt types in Table 2-13.

2.9.2 Misaligned Instruction Fetch Syndrome

The ESR[MIF] bit indicates an Instruction Storage Interrupt caused by an attempt to fetch an instruction from a Book E page that is not aligned on a word boundary. The fetch may have been caused by one of the following:

• Execution of a Branch to LR instruction with LR[62]=1

• A Branch to CTR instruction with CTR[62]=1

• Execution of an rfi or se_rfi instruction with SRR0[62]=1

• Execution of an rfci or se_rfci instruction with CSRR0[62]=1

• Execution of an rfdi or se_rfdi instruction with DSRR0[62]=1, where the destination address corresponds to an instruction page not marked as a VLE page.

The ESR[MIF] bit also indicates an Instruction TLB Interrupt caused by a TLB miss on the second half of a misaligned 32-bit VLE Instruction. SRR0 points to the first half of the instruction, which resides on the previous page from the miss at page offset 0xFFE. The ITLB handler may need to note that the miss corresponds to the next page, although MMU MAS2 contents correctly reflect the page corresponding to the miss.

2.9.3 Precise External Termination Error Syndrome

The ESR[XTE] bit indicates a precise external termination error DSI or ISI interrupt caused by an instruction. This syndrome bit is set on an external termination error exception reported in a precise way via a DSI or ISI as opposed to a machine check.

58 VLEMI VLE mode instruction SPE unavailable, SPE floating-point data exception, SPE floating-point round exception, data storage, data TLB, instruction storage, alignment, program, and system call

59–61 — Reserved, should be cleared. —

62 MIF Misaligned instruction fetch Instruction storage, instruction TLB 63 XTE External termination error (precise) Data storage, instruction storage

1 When optional cache is present. Unused on e200z3.

Table 2-13. ESR Field Descriptions (continued)

Bits Name Description Associated Interrupt Type

2.9.4 e200z3-Specific Interrupt Registers

In addition to the Book E-defined interrupt registers, the e200z3 implements DSRR0 and DSRR1 to facilitate handling debug interrupts and the EIS-defined MCSR to facilitate handling machine check interrupts.

2.9.4.1 Debug Save/Restore Register 0 (DSRR0)

During a debug interrupt, DSRR0, shown in Figure 2-19, holds the address of the instruction where the interrupted process should resume. The instruction is interrupt-specific; see Section 4.6.16, “Debug Interrupt (IVOR15),” and particularly Table 4-25. When rfdi executes, instruction execution continues at the address in DSRR0. DSRR0 and DSRR1 are not affected by rfi or rfci.

2.9.4.2 Debug Save/Restore Register 1 (DSRR1)

DSRR1, shown in Figure 2-20, saves and restores machine state during debug interrupts. MSR contents are placed into DSRR1. When rfdi executes, the contents of DSRR1 are restored into MSR. DSRR1 bits that correspond to reserved MSR bits are also reserved. (See Section 2.4.1, “Machine State Register (MSR).”) DSRR0 and DSRR1 are not affected by rfi or rfci. Reserved MSR bits can be altered by rfi, rfci, or rfdi.

2.9.4.3 Machine Check Syndrome Register (MCSR)

When the core complex takes a machine check interrupt, it updates the machine check syndrome register (MCSR) to differentiate between machine check conditions. The MCSR is shown in Figure 2-21.

32 63

Field Next instruction address

Reset Undefined on m_por assertion, unchanged on p_reset_b assertion

R/W R/W

SPR SPR 574

Figure 2-19. Debug Save/Restore Register 0 (DSRR0)

32 63

Field MSR state information

Reset Undefined on m_por assertion, unchanged on p_reset_b assertion

R/W R/W

SPR SPR 575

Figure 2-20. Debug Save/Restore Register 1 (DSRR1)

MCSR fields, described in Table 2-14, indicate whether the source of a machine check condition is recoverable. When an MCSR bit is set, the core complex asserts p_mcp_out for system information.